| Message ID | 20231005160701.19987-5-dustin@howett.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | cros_ec: add support for newer versions of the Framework Laptop | expand |
On Thu, Oct 05, 2023 at 11:07:01AM -0500, Dustin L. Howett wrote: > - CROS_EC_LPC_QUIRK_SHORT_HOSTCMD_RESERVATION: only attempt to reserve > 0xff (rather than 0x100) I/O ports for the host command region What if it still reserves 0x100 I/O ports for these deivces? > @@ -34,6 +34,27 @@ > /* True if ACPI device is present */ > static bool cros_ec_lpc_acpi_device_found; > > +/* If this quirk is enabled, the driver will only reserve 0xFF I/O ports > + * (rather than 0x100) for the host command mapped memory region. > + */ [...] > +/* If this quirk is enabled, lpc_driver_data.quirk_mmio_memory_base will be used > + * as the base port for EC mapped memory. > + */ See https://www.kernel.org/doc/html/latest/process/coding-style.html#commenting > @@ -363,14 +384,32 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) > acpi_status status; > struct cros_ec_device *ec_dev; > struct cros_ec_lpc *ec_lpc; > + struct lpc_driver_data *driver_data; > + int region1_size; > u8 buf[2] = {}; > int irq, ret; > + u32 quirks = 0; > > ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL); > if (!ec_lpc) > return -ENOMEM; > > ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP; > + region1_size = EC_HOST_CMD_REGION_SIZE; `quirks` doesn't need to initialize; or move it to a more limited scope. Instead, `region1_size` can just initialize to EC_HOST_CMD_REGION_SIZE.
On 2023-10-05 11:07:01-0500, Dustin L. Howett wrote: > Some devices ship a ChromeOS EC in a non-standard configuration; quirks > allow cros_ec_lpc to account for these non-standard configurations. > > It supports the following quirks: > - CROS_EC_LPC_QUIRK_REMAP_MEMORY: use a different port I/O base for > MMIO to the EC's memory region > - CROS_EC_LPC_QUIRK_SHORT_HOSTCMD_RESERVATION: only attempt to reserve > 0xff (rather than 0x100) I/O ports for the host command region > > Signed-off-by: Dustin L. Howett <dustin@howett.net> [..] > + > + driver_data = platform_get_drvdata(pdev); > + if (driver_data) { > + quirks = driver_data->quirks; > + > + if (quirks) > + dev_warn(dev, "loaded with quirks %8.08x\n", quirks); dev_warn() is too loud. [..]
diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index ef7943e6a01d..c06575625d2f 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -34,6 +34,27 @@ /* True if ACPI device is present */ static bool cros_ec_lpc_acpi_device_found; +/* If this quirk is enabled, the driver will only reserve 0xFF I/O ports + * (rather than 0x100) for the host command mapped memory region. + */ +#define CROS_EC_LPC_QUIRK_SHORT_HOSTCMD_RESERVATION BIT(0) +/* If this quirk is enabled, lpc_driver_data.quirk_mmio_memory_base will be used + * as the base port for EC mapped memory. + */ +#define CROS_EC_LPC_QUIRK_REMAP_MEMORY BIT(1) + +/** + * struct lpc_driver_data - driver data attached to a DMI device ID to indicate + * hardware quirks. + * @quirks: a bitfield composed of quirks from CROS_EC_LPC_QUIRK_* + * @quirk_mmio_memory_base: The first I/O port addressing EC mapped memory (used + * when quirks (...REMAP_MEMORY) is set. + */ +struct lpc_driver_data { + u32 quirks; + u16 quirk_mmio_memory_base; +}; + /** * struct cros_ec_lpc - LPC device-specific data * @mmio_memory_base: The first I/O port addressing EC mapped memory. @@ -363,14 +384,32 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) acpi_status status; struct cros_ec_device *ec_dev; struct cros_ec_lpc *ec_lpc; + struct lpc_driver_data *driver_data; + int region1_size; u8 buf[2] = {}; int irq, ret; + u32 quirks = 0; ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL); if (!ec_lpc) return -ENOMEM; ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP; + region1_size = EC_HOST_CMD_REGION_SIZE; + + driver_data = platform_get_drvdata(pdev); + if (driver_data) { + quirks = driver_data->quirks; + + if (quirks) + dev_warn(dev, "loaded with quirks %8.08x\n", quirks); + + if (quirks & CROS_EC_LPC_QUIRK_REMAP_MEMORY) + ec_lpc->mmio_memory_base = driver_data->quirk_mmio_memory_base; + + if (quirks & CROS_EC_LPC_QUIRK_SHORT_HOSTCMD_RESERVATION) + region1_size -= 1; + } /* * The Framework Laptop (and possibly other non-ChromeOS devices) @@ -420,7 +459,7 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) return -EBUSY; } if (!devm_request_region(dev, EC_HOST_CMD_REGION1, - EC_HOST_CMD_REGION_SIZE, dev_name(dev))) { + region1_size, dev_name(dev))) { dev_err(dev, "couldn't reserve region1\n"); return -EBUSY; }
Some devices ship a ChromeOS EC in a non-standard configuration; quirks allow cros_ec_lpc to account for these non-standard configurations. It supports the following quirks: - CROS_EC_LPC_QUIRK_REMAP_MEMORY: use a different port I/O base for MMIO to the EC's memory region - CROS_EC_LPC_QUIRK_SHORT_HOSTCMD_RESERVATION: only attempt to reserve 0xff (rather than 0x100) I/O ports for the host command region Signed-off-by: Dustin L. Howett <dustin@howett.net> --- drivers/platform/chrome/cros_ec_lpc.c | 41 ++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-)