From patchwork Fri May 3 18:18:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 13653380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 768A0C10F16 for ; Fri, 3 May 2024 19:31:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KaBkDO8FHRhIHia83RR3i4jDd/fZ+6OrWPMlt2nPDQA=; b=rK8zR/JmCxshkk YfFg0BpTCBPwORvL77ajp1a0NzoDSl1P3/OfSCquP17Pvg3nZYzeHVA6Q4uKz3iCQxJE27CMCmZls mSuFz5ZqV1782MDnz7Cqta+HGkE9l/2nLQ01RebGLdRY4NPazY3mHcr1gUxUBg3328YaVHpHscI+4 FL9dquES0u77G+ltzKsmxDZG3H/KL3SJ8VY7txB7MpmMeCrQLwDciAFt5m/7bSJAQ+C10bvpUmto2 VgZDXSPrHkRytjgEv/noum4mqyps3XqxKNmnQzsV9o2Fcr9U3Pe1cfVbkxPzCcTXqQBmV/l54tkvm VzL1uoN7L3bCi8hhcvKA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2yd5-00000000Ako-3OsW; Fri, 03 May 2024 19:31:35 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2xUt-0000000HX06-0VLg for linux-arm-kernel@bombadil.infradead.org; Fri, 03 May 2024 18:19:03 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Cc:To:In-Reply-To:References: Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Sender:Reply-To:Content-ID:Content-Description; bh=cH3YNCAT0dZmAgzMEs/mp+5fGn0LRaZcONh2CiROrH4=; b=l9De78fhXxxTjYcdKECSWuEbPY tQmk8JWXGk09IN9rD0h4yMB/lRrhG6HJvOTjGeff2F4/RGQO/JeFm61MDtTAJUy7YPQRE5xjF2fnB MorpkAk43ryVe/unCuOLCqxnsN2tJfcx/Lt1Dbo/GycrMhd2tvdFRZUKqGCUE65QcVLudtjAGO3uX Gqm0VCA5D53Ypp3rsorzItOzHbIM16m/2VVuGuai7tJp35YHeaNV80C3TZ9oiTvA0lddkWlhM33As M5ssKJRTp8PXvmlv/uRySXuujhr4pCvvpAs6FkH1spmKWPzRZKaQZ+f3YRNjuLn3X13eMsuqUOdkM /Nbs/YNA==; Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2xUo-00000000drA-2ITL for linux-arm-kernel@lists.infradead.org; Fri, 03 May 2024 18:19:01 +0000 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-6f3e3d789cdso8825b3a.1 for ; Fri, 03 May 2024 11:18:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1714760337; x=1715365137; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cH3YNCAT0dZmAgzMEs/mp+5fGn0LRaZcONh2CiROrH4=; b=FuRtTobH3lXkeZw/FarXEud3O9oT8IgXtqIuGwdnN9680mXKwX7kKAT2jB3r3RTSsJ keCvwj6//YaE6qJeazRCJTK+9gB666Yd30pZZAHdYWUR63RtVGIANXAUpgr2z1xXGMyo oHdPYOUIUN2U2dU8shZKWXSq7pMllxZ2aD31zlRuQXIVvCVLML9OPdAFonZ2NuAntAm1 GJCuyGgWkBCOpQjhOxdHckIIw/vhAmj/BcYq9Y+TKGRNfyY7RFfgn6t0of/5PgLlso4U CSCPKxCvcgBo9IHoiNjR5IkIKSiUtlqVXM0fPqput10WB4U+3EWw5doEnjdyiQsw44EF 7dsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714760337; x=1715365137; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cH3YNCAT0dZmAgzMEs/mp+5fGn0LRaZcONh2CiROrH4=; b=g4cF2wX/5rdvYdFPZnJzf99R8GAihCIxkheZDo3TkBEedAKdstHL1wYTc330wOISik +qjSpqGRZeli5FI54yY2pEjjQ3z3iXr4XmF5SUfy1lXsmJ5XRXxup7278oLnLTt2iHGs 20Rn9lU40s8yanNicvYaWunuaxBhiBerb0Eg/9KWNpB0miSLCfhWYp/jRY/UCx+mJg3w TSdIjkl+f+rEV/ywX10z7VSrfdnFeQ152pgtXrXz7PigIXORCMCDs4kqUA1MO7S3f8AR 6rX5MhftEd8CPz8aInt3R/LND0prRltCmb4qw2jzWuvvoS/utcV68aVZXxRqTaeyRqpx 9J+w== X-Forwarded-Encrypted: i=1; AJvYcCUS2niNfJcq2m/mj3f/WrvHWeI+MsEJnnp10fNuFxkeq6XecVMcjLzQvvB8mDGOpJHA2sldqmsJbhHazHeCjsvOijhhq+tW1AspUBrdg5+meScIDEM= X-Gm-Message-State: AOJu0YzUaQ5ZMzBZ3MwXE+lkzui2Ln8HakZrKq+HLixAEL/u3dcW/xRm kYhSu0T6WH0xRQNAAZEt9xmEY/ml6526spC5cfuNTU66jCPa60OkoQG9d+YjHUk= X-Google-Smtp-Source: AGHT+IGZUjk8whSVM3IbmFOtPtzVfpNDmJmpbJU6d7XZ6P4ZdQPc4Z+JMmnpQ9/t0xUjKfu7KDm8VQ== X-Received: by 2002:a05:6a20:321b:b0:1a7:9afe:2f48 with SMTP id hl27-20020a056a20321b00b001a79afe2f48mr3446861pzc.27.1714760336942; Fri, 03 May 2024 11:18:56 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id fu6-20020a056a00610600b006f3f5d3595fsm3355421pfb.80.2024.05.03.11.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 May 2024 11:18:56 -0700 (PDT) From: Charlie Jenkins Date: Fri, 03 May 2024 11:18:22 -0700 Subject: [PATCH v6 07/17] riscv: Introduce vendor variants of extension helpers MIME-Version: 1.0 Message-Id: <20240503-dev-charlie-support_thead_vector_6_9-v6-7-cb7624e65d82@rivosinc.com> References: <20240503-dev-charlie-support_thead_vector_6_9-v6-0-cb7624e65d82@rivosinc.com> In-Reply-To: <20240503-dev-charlie-support_thead_vector_6_9-v6-0-cb7624e65d82@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Shuah Khan Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714760318; l=9175; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=oHywOTliEHoaGOH+p/KAB2oes75uvxzplJdN2OqqeZo=; b=KbC1XYFNhZNBKPSNnQjD1psZt+bhKOmWaPHv/jdTf/wZGgSULD+X0+D7wK/zDphb/wmo3WY/Q awSZL38TAKpDsC86G6cf3ajysrmwSOYgS0Ch2yRXpUwemhXb4uqF+/3 X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240503_191858_889166_32F93102 X-CRM114-Status: GOOD ( 21.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Vendor extensions are maintained in per-vendor structs (separate from standard extensions which live in riscv_isa). Create vendor variants for the existing extension helpers to interface with the riscv_isa_vendor bitmaps. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/errata/sifive/errata.c | 3 + arch/riscv/errata/thead/errata.c | 3 + arch/riscv/include/asm/vendor_extensions.h | 97 ++++++++++++++++++++++++++++++ arch/riscv/kernel/cpufeature.c | 32 +++++++--- arch/riscv/kernel/vendor_extensions.c | 40 ++++++++++++ 5 files changed, 167 insertions(+), 8 deletions(-) diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c index 3d9a32d791f7..b68b023115c2 100644 --- a/arch/riscv/errata/sifive/errata.c +++ b/arch/riscv/errata/sifive/errata.c @@ -12,6 +12,7 @@ #include #include #include +#include struct errata_info_t { char name[32]; @@ -91,6 +92,8 @@ void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, u32 cpu_apply_errata = 0; u32 tmp; + BUILD_BUG_ON(ERRATA_SIFIVE_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return; diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index b1c410bbc1ae..6d5d7f8eebbc 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -18,6 +18,7 @@ #include #include #include +#include static bool errata_probe_pbmt(unsigned int stage, unsigned long arch_id, unsigned long impid) @@ -160,6 +161,8 @@ void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, u32 tmp; void *oldptr, *altptr; + BUILD_BUG_ON(ERRATA_THEAD_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + for (alt = begin; alt < end; alt++) { if (alt->vendor_id != THEAD_VENDOR_ID) continue; diff --git a/arch/riscv/include/asm/vendor_extensions.h b/arch/riscv/include/asm/vendor_extensions.h index bf4dac66e6e6..a6959836f895 100644 --- a/arch/riscv/include/asm/vendor_extensions.h +++ b/arch/riscv/include/asm/vendor_extensions.h @@ -31,4 +31,101 @@ extern struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[]; extern const size_t riscv_isa_vendor_ext_list_size; +/* + * The alternatives need some way of distinguishing between vendor extensions + * and errata. Incrementing all of the vendor extension keys so they are at + * least 0x8000 accomplishes that. + */ +#define RISCV_VENDOR_EXT_ALTERNATIVES_BASE 0x8000 + +#define VENDOR_EXT_ALL_CPUS -1 + +bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsigned int bit); +#define riscv_cpu_isa_vendor_extension_available(cpu, vendor, ext) \ + __riscv_isa_vendor_extension_available(cpu, vendor, RISCV_ISA_VENDOR_EXT_##ext) +#define riscv_isa_vendor_extension_available(vendor, ext) \ + __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, \ + RISCV_ISA_VENDOR_EXT_##ext) + +static __always_inline bool __riscv_has_extension_likely(const unsigned long vendor, + const unsigned long ext) +{ + asm goto(ALTERNATIVE("j %l[l_no]", "nop", %[vendor], %[ext], 1) + : + : [vendor] "i" (vendor), [ext] "i" (ext) + : + : l_no); + + return true; +l_no: + return false; +} + +static __always_inline bool __riscv_has_extension_unlikely(const unsigned long vendor, + const unsigned long ext) +{ + asm goto(ALTERNATIVE("nop", "j %l[l_yes]", %[vendor], %[ext], 1) + : + : [vendor] "i" (vendor), [ext] "i" (ext) + : + : l_yes); + + return false; +l_yes: + return true; +} + +static __always_inline bool riscv_has_vendor_extension_likely(const unsigned long vendor, + const unsigned long ext) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) + return false; + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) + return __riscv_has_extension_likely(vendor, + ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + + return __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, ext); +} + +static __always_inline bool riscv_has_vendor_extension_unlikely(const unsigned long vendor, + const unsigned long ext) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) + return false; + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) + return __riscv_has_extension_unlikely(vendor, + ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + + return __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, ext); +} + +static __always_inline bool riscv_cpu_has_vendor_extension_likely(const unsigned long vendor, + int cpu, const unsigned long ext) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) + return false; + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && + __riscv_has_extension_likely(vendor, ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE)) + return true; + + return __riscv_isa_vendor_extension_available(cpu, vendor, ext); +} + +static __always_inline bool riscv_cpu_has_vendor_extension_unlikely(const unsigned long vendor, + int cpu, + const unsigned long ext) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) + return false; + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && + __riscv_has_extension_unlikely(vendor, ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE)) + return true; + + return __riscv_isa_vendor_extension_available(cpu, vendor, ext); +} + #endif /* _ASM_VENDOR_EXTENSIONS_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 6019b2527c46..2a5527020d0f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -864,25 +864,41 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, { struct alt_entry *alt; void *oldptr, *altptr; - u16 id, value; + u16 id, value, vendor; if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return; for (alt = begin; alt < end; alt++) { - if (alt->vendor_id != 0) - continue; - id = PATCH_ID_CPUFEATURE_ID(alt->patch_id); + vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id); - if (id >= RISCV_ISA_EXT_MAX) { + /* + * Any alternative with a patch_id that is less than + * RISCV_ISA_EXT_MAX is interpreted as a standard extension. + * + * Any alternative with patch_id that is greater than or equal + * to RISCV_VENDOR_EXT_ALTERNATIVES_BASE is interpreted as a + * vendor extension. + */ + if (id < RISCV_ISA_EXT_MAX) { + /* + * This patch should be treated as errata so skip + * processing here. + */ + if (alt->vendor_id != 0) + continue; + + if (!__riscv_isa_extension_available(NULL, id)) + continue; + } else if (id >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE) { + if (!__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, id)) + continue; + } else { WARN(1, "This extension id:%d is not in ISA extension list", id); continue; } - if (!__riscv_isa_extension_available(NULL, id)) - continue; - value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id); if (!riscv_cpufeature_patch_check(id, value)) continue; diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c index 03ba7949a07f..e4ef574b7d08 100644 --- a/arch/riscv/kernel/vendor_extensions.c +++ b/arch/riscv/kernel/vendor_extensions.c @@ -3,6 +3,7 @@ * Copyright 2024 Rivos, Inc */ +#include #include #include @@ -16,3 +17,42 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = { }; const size_t riscv_isa_vendor_ext_list_size = ARRAY_SIZE(riscv_isa_vendor_ext_list); + +/** + * __riscv_isa_vendor_extension_available() - Check whether given vendor + * extension is available or not. + * + * @cpu: check if extension is available on this cpu + * @vendor: vendor that the extension is a member of + * @bit: bit position of the desired extension + * Return: true or false + * + * NOTE: When cpu is -1, will check if extension is available on all cpus + */ +bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsigned int bit) +{ + unsigned long *bmap; + struct riscv_isainfo *cpu_bmap; + size_t bmap_size; + + switch (vendor) { +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD + case THEAD_VENDOR_ID: + bmap = riscv_isa_vendor_ext_list_thead.vendor_bitmap; + cpu_bmap = riscv_isa_vendor_ext_list_thead.per_hart_vendor_bitmap; + bmap_size = riscv_isa_vendor_ext_list_thead.bitmap_size; + break; +#endif + default: + return false; + } + + if (cpu != -1) + bmap = cpu_bmap[cpu].isa; + + if (bit >= bmap_size) + return false; + + return test_bit(bit, bmap) ? true : false; +} +EXPORT_SYMBOL_GPL(__riscv_isa_vendor_extension_available);