| Message ID | ea2e786eda4561cb5d11b62a4edd7e75c0975f1f.1714513773.git.daniel@makrotopia.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | dt-bindings: net: mediatek: remove wrongly added clocks and SerDes | expand |
On Tue, Apr 30, 2024 at 10:53:55PM +0100, Daniel Golle wrote: > Several clocks as well as both sgmiisys phandles were added by mistake > to the Ethernet bindings for MT7988. > > This happened because the vendor driver which served as a reference uses > a high number of syscon phandles to access various parts of the SoC > which wasn't acceptable upstream. Hence several parts which have never > previously been supported (such SerDes PHY and USXGMII PCS) are going to > be implemented by separate drivers. As a result the device tree will > look much more sane. > > Quickly align the bindings with the upcoming reality of the drivers > actually adding support for the remaining Ethernet-related features of > the MT7988 SoC. > > Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding") > Signed-off-by: Daniel Golle <daniel@makrotopia.org> > --- > .../devicetree/bindings/net/mediatek,net.yaml | 32 ++++--------------- > 1 file changed, 7 insertions(+), 25 deletions(-) > > diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml > index e74502a0afe8..030d106bc7d3 100644 > --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml > +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml > @@ -337,32 +337,23 @@ allOf: > minItems: 4 > > clocks: > - minItems: 34 > - maxItems: 34 > + minItems: 24 > + maxItems: 24 > > clock-names: > items: > - - const: crypto > + - const: xgp1 > + - const: xgp2 > + - const: xgp3 Why is the ordering changing too? > - const: fe > - const: gp2 > - const: gp1 > - const: gp3 > + - const: esw > + - const: crypto > - const: ethwarp_wocpu2 > - const: ethwarp_wocpu1 > - const: ethwarp_wocpu0 > - - const: esw > - - const: netsys0 > - - const: netsys1 > - - const: sgmii_tx250m > - - const: sgmii_rx250m > - - const: sgmii2_tx250m > - - const: sgmii2_rx250m > - - const: top_usxgmii0_sel > - - const: top_usxgmii1_sel > - - const: top_sgm0_sel > - - const: top_sgm1_sel > - - const: top_xfi_phy0_xtal_sel > - - const: top_xfi_phy1_xtal_sel > - const: top_eth_gmii_sel > - const: top_eth_refck_50m_sel > - const: top_eth_sys_200m_sel > @@ -375,15 +366,6 @@ allOf: > - const: top_netsys_sync_250m_sel > - const: top_netsys_ppefb_250m_sel > - const: top_netsys_warp_sel > - - const: wocpu1 > - - const: wocpu0 > - - const: xgp1 > - - const: xgp2 > - - const: xgp3 > - > - mediatek,sgmiisys: > - minItems: 2 > - maxItems: 2 > > patternProperties: > "^mac@[0-1]$": > -- > 2.44.0 >
diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml index e74502a0afe8..030d106bc7d3 100644 --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml @@ -337,32 +337,23 @@ allOf: minItems: 4 clocks: - minItems: 34 - maxItems: 34 + minItems: 24 + maxItems: 24 clock-names: items: - - const: crypto + - const: xgp1 + - const: xgp2 + - const: xgp3 - const: fe - const: gp2 - const: gp1 - const: gp3 + - const: esw + - const: crypto - const: ethwarp_wocpu2 - const: ethwarp_wocpu1 - const: ethwarp_wocpu0 - - const: esw - - const: netsys0 - - const: netsys1 - - const: sgmii_tx250m - - const: sgmii_rx250m - - const: sgmii2_tx250m - - const: sgmii2_rx250m - - const: top_usxgmii0_sel - - const: top_usxgmii1_sel - - const: top_sgm0_sel - - const: top_sgm1_sel - - const: top_xfi_phy0_xtal_sel - - const: top_xfi_phy1_xtal_sel - const: top_eth_gmii_sel - const: top_eth_refck_50m_sel - const: top_eth_sys_200m_sel @@ -375,15 +366,6 @@ allOf: - const: top_netsys_sync_250m_sel - const: top_netsys_ppefb_250m_sel - const: top_netsys_warp_sel - - const: wocpu1 - - const: wocpu0 - - const: xgp1 - - const: xgp2 - - const: xgp3 - - mediatek,sgmiisys: - minItems: 2 - maxItems: 2 patternProperties: "^mac@[0-1]$":
Several clocks as well as both sgmiisys phandles were added by mistake to the Ethernet bindings for MT7988. This happened because the vendor driver which served as a reference uses a high number of syscon phandles to access various parts of the SoC which wasn't acceptable upstream. Hence several parts which have never previously been supported (such SerDes PHY and USXGMII PCS) are going to be implemented by separate drivers. As a result the device tree will look much more sane. Quickly align the bindings with the upcoming reality of the drivers actually adding support for the remaining Ethernet-related features of the MT7988 SoC. Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding") Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- .../devicetree/bindings/net/mediatek,net.yaml | 32 ++++--------------- 1 file changed, 7 insertions(+), 25 deletions(-)