From patchwork Tue Apr 30 12:01:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13648870 X-Patchwork-Delegate: manivannanece23@gmail.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CE9513D289; Tue, 30 Apr 2024 12:02:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714478551; cv=none; b=SLVmNYmXb2VysNB14vow8STZ7Zn3h36QQN/KWgSHzrDJNvx3aajWS5aFjJJTOJ/JOKEzuvax2jYoHx1eaafpfnSDw1PxKjaRB7cvrngHPVHzniKgm8/9xkz/Tf0NI3fBRkHNwwPJCfo6d6KeouSb6fc5J4974lT783zxWyJTAIo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714478551; c=relaxed/simple; bh=FF5kjYOiGGFH7JDZ21aiyiTHxQMew/SAJYkr6QWZ3L0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q5l5/QU+FWhL7bZFW4hSTDObxMSq/IKyXnag6c371dGoPk0yhr9LWCss2zfMfeSGWg967zFwocVZAHw9ADp9jZWwSRCfmqQ/ieNbLQY4lNrZm1V+5AzC3jy0j995yOgeO3dOEGGPvsyGdN8tSUSYAQiU9vse/X8Bd9GYToCydCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KcaGiXU4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KcaGiXU4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3A2E3C4AF1C; Tue, 30 Apr 2024 12:02:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1714478551; bh=FF5kjYOiGGFH7JDZ21aiyiTHxQMew/SAJYkr6QWZ3L0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KcaGiXU402q2xQs1/uLSZa/2IXGGF1G1oar16jKhwao5h/3LvE1Cr8fpKyoOQeogD 3+76kl+NvaU+nVPkuWi+zhdQ5NOUBJJfFqbzz94OTjWDgWcyAW/Uvph7SUWZRdv4nv i1S9f5Y4Uhem+EEbjhh7YquW7EAEFgoNdQsHZKBw97txvORKVhRMqBQJcoZleVecrN UL5S2CCqB5+BHMz8zfsa1XMQ+rbwiMZquwAZzTwvElOKQ4eUrXh7FiZq/USfbGOQGS dnfA50YMvZ/jqfrwHhdYb17cPtE/sslhfzBqKw5SSJRlBf3l9Tp8zBxoi2rKiO/3zi h3Z8JkTXyEPuA== From: Niklas Cassel Date: Tue, 30 Apr 2024 14:01:05 +0200 Subject: [PATCH v2 08/14] PCI: dw-rockchip: Add rockchip_pcie_ltssm() helper Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-rockchip-pcie-ep-v1-v2-8-a0f5ee2a77b6@kernel.org> References: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> In-Reply-To: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1425; i=cassel@kernel.org; h=from:subject:message-id; bh=FF5kjYOiGGFH7JDZ21aiyiTHxQMew/SAJYkr6QWZ3L0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIM7m7Yto2TsXXa9x3nrPfs9TMQ+7DrU/zR4y1KWS5nS m8rMOhd7ihlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBEPiQyMnzQyH+4l3d+9dO9 is6/p825cCD4fILegV/LHr1UDn45v7CQkaHD4/Uc7t3c2tf9Tzf/05NtSIi8spShnfXWdOWM6ni GU8wA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Add a rockchip_pcie_ltssm() helper function that reads the LTSSM status. This helper will be used in additional places in follow-up patches. Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 1993c430b90c..4023fd86176f 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -143,6 +143,11 @@ static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) return 0; } +static inline u32 rockchip_pcie_ltssm(struct rockchip_pcie *rockchip) +{ + return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS); +} + static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) { rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, @@ -152,7 +157,7 @@ static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) static int rockchip_pcie_link_up(struct dw_pcie *pci) { struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); - u32 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS); + u32 val = rockchip_pcie_ltssm(rockchip); if ((val & PCIE_LINKUP) == PCIE_LINKUP && (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY)