[1/1] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Commit Message

Daniel Henrique Barboza May 16, 2024, 5:10 p.m. UTC

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

Cc: Akihiko Odaki <[e-mail]>
Cc: Alex Bennée <[e-mail]>
Reported-by: Robin Dapp <[e-mail]>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <[e-mail]>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

LIU Zhiwei May 17, 2024, 1:04 a.m. UTC | #1

On 2024/5/17 1:10, Daniel Henrique Barboza wrote:
> Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
> in bytes, when in this context we want 'reg_width' as the length in
> bits.
>
> Fix 'reg_width' back to the value in bits like 7cb59921c05a
> ("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
> beforehand.
>
> Cc: Akihiko Odaki <[e-mail]>
> Cc: Alex Bennée <[e-mail]>
> Reported-by: Robin Dapp <[e-mail]>
> Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
> Signed-off-by: Daniel Henrique Barboza <[e-mail]>

Reviewed-by: LIU Zhiwei <[e-mail]>

Zhiwei

> ---
>   target/riscv/gdbstub.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index d0cc5762c2..358158c42a 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -288,7 +288,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
>   static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
>   {
>       RISCVCPU *cpu = RISCV_CPU(cs);
> -    int reg_width = cpu->cfg.vlenb;
> +    int reg_width = cpu->cfg.vlenb << 3;
>       GDBFeatureBuilder builder;
>       int i;
>

Alex Bennée May 17, 2024, 5:56 p.m. UTC | #2

Daniel Henrique Barboza <[e-mail]> writes:

> Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
> in bytes, when in this context we want 'reg_width' as the length in
> bits.
>
> Fix 'reg_width' back to the value in bits like 7cb59921c05a
> ("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
> beforehand.
>
> Cc: Akihiko Odaki <[e-mail]>
> Cc: Alex Bennée <[e-mail]>
> Reported-by: Robin Dapp <[e-mail]>
> Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
> Signed-off-by: Daniel Henrique Barboza <[e-mail]>
> ---
>  target/riscv/gdbstub.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index d0cc5762c2..358158c42a 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -288,7 +288,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
>  static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
>  {
>      RISCVCPU *cpu = RISCV_CPU(cs);
> -    int reg_width = cpu->cfg.vlenb;
> +    int reg_width = cpu->cfg.vlenb << 3;

You could consider renaming the var to reg_bits for clarity but
otherwise:

Acked-by: Alex Bennée <[e-mail]>


>      GDBFeatureBuilder builder;
>      int i;

Patch

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index d0cc5762c2..358158c42a 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -288,7 +288,7 @@  static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int reg_width = cpu->cfg.vlenb << 3;
     GDBFeatureBuilder builder;
     int i;