| Message ID | 20240502143410.12629-2-prajna.rajendrakumar@microchip.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for GPIO based CS | expand |
On Thu, May 02, 2024 at 03:34:08PM +0100, Prajna Rajendra Kumar wrote: > The SPI controller within the PolarFire SoC is capable of handling > multiple CS, but only one CS line is wired in the MSS. Therefore, > use GPIO descriptors to configure additional CS lines. > > Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
Hi Prajna,
kernel test robot noticed the following build warnings:
[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on robh/for-next krzk-dt/for-next linus/master v6.9-rc6 next-20240502]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Prajna-Rajendra-Kumar/spi-spi-microchip-core-Add-support-for-GPIO-based-CS/20240502-223714
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20240502143410.12629-2-prajna.rajendrakumar%40microchip.com
patch subject: [PATCH 1/3] spi: spi-microchip-core: Add support for GPIO based CS
config: arm-randconfig-002-20240503 (https://download.01.org/0day-ci/archive/20240503/202405031328.ljBB1tMb-lkp@intel.com/config)
compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project 37ae4ad0eef338776c7e2cffb3896153d43dcd90)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240503/202405031328.ljBB1tMb-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405031328.ljBB1tMb-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/spi/spi-microchip-core.c:21:
In file included from include/linux/spi/spi.h:17:
In file included from include/linux/scatterlist.h:8:
In file included from include/linux/mm.h:2208:
include/linux/vmstat.h:522:36: warning: arithmetic between different enumeration types ('enum node_stat_item' and 'enum lru_list') [-Wenum-enum-conversion]
522 | return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_"
| ~~~~~~~~~~~ ^ ~~~
>> drivers/spi/spi-microchip-core.c:261:11: warning: address of array 'spi->cs_gpiod' will always evaluate to 'true' [-Wpointer-bool-conversion]
261 | if (spi->cs_gpiod)
| ~~ ~~~~~^~~~~~~~
2 warnings generated.
vim +261 drivers/spi/spi-microchip-core.c
255
256 static int mchp_corespi_setup(struct spi_device *spi)
257 {
258 struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);
259 u32 reg;
260
> 261 if (spi->cs_gpiod)
262 return 0;
263
264 /*
265 * Active high targets need to be specifically set to their inactive
266 * states during probe by adding them to the "control group" & thus
267 * driving their select line low.
268 */
269 if (spi->mode & SPI_CS_HIGH) {
270 reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
271 reg |= BIT(spi_get_chipselect(spi, 0));
272 mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
273 }
274 return 0;
275 }
276
Hi Prajna, kernel test robot noticed the following build warnings: [auto build test WARNING on broonie-spi/for-next] [also build test WARNING on robh/for-next krzk-dt/for-next linus/master v6.9-rc6 next-20240502] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Prajna-Rajendra-Kumar/spi-spi-microchip-core-Add-support-for-GPIO-based-CS/20240502-223714 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next patch link: https://lore.kernel.org/r/20240502143410.12629-2-prajna.rajendrakumar%40microchip.com patch subject: [PATCH 1/3] spi: spi-microchip-core: Add support for GPIO based CS config: sh-allmodconfig (https://download.01.org/0day-ci/archive/20240503/202405031322.8UuTAWrf-lkp@intel.com/config) compiler: sh4-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240503/202405031322.8UuTAWrf-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202405031322.8UuTAWrf-lkp@intel.com/ All warnings (new ones prefixed by >>): drivers/spi/spi-microchip-core.c: In function 'mchp_corespi_setup': >> drivers/spi/spi-microchip-core.c:261:13: warning: the comparison will always evaluate as 'true' for the address of 'cs_gpiod' will never be NULL [-Waddress] 261 | if (spi->cs_gpiod) | ^~~ In file included from drivers/spi/spi-microchip-core.c:21: include/linux/spi/spi.h:219:34: note: 'cs_gpiod' declared here 219 | struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select gpio desc */ | ^~~~~~~~ vim +261 drivers/spi/spi-microchip-core.c 255 256 static int mchp_corespi_setup(struct spi_device *spi) 257 { 258 struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller); 259 u32 reg; 260 > 261 if (spi->cs_gpiod) 262 return 0; 263 264 /* 265 * Active high targets need to be specifically set to their inactive 266 * states during probe by adding them to the "control group" & thus 267 * driving their select line low. 268 */ 269 if (spi->mode & SPI_CS_HIGH) { 270 reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT); 271 reg |= BIT(spi_get_chipselect(spi, 0)); 272 mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg); 273 } 274 return 0; 275 } 276
diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c index 634364c7cfe6..71886c27bca3 100644 --- a/drivers/spi/spi-microchip-core.c +++ b/drivers/spi/spi-microchip-core.c @@ -258,6 +258,9 @@ static int mchp_corespi_setup(struct spi_device *spi) struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller); u32 reg; + if (spi->cs_gpiod) + return 0; + /* * Active high targets need to be specifically set to their inactive * states during probe by adding them to the "control group" & thus @@ -516,6 +519,7 @@ static int mchp_corespi_probe(struct platform_device *pdev) host->num_chipselect = num_cs; host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + host->use_gpio_descriptors = true; host->setup = mchp_corespi_setup; host->bits_per_word_mask = SPI_BPW_MASK(8); host->transfer_one = mchp_corespi_transfer_one;
The SPI controller within the PolarFire SoC is capable of handling multiple CS, but only one CS line is wired in the MSS. Therefore, use GPIO descriptors to configure additional CS lines. Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com> --- drivers/spi/spi-microchip-core.c | 4 ++++ 1 file changed, 4 insertions(+)