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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id ah2-20020a1709069ac200b00a4e393b6349sm13898875ejc.5.2024.04.29.08.16.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 08:16:27 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 73c0a8fd-063b-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1714403788; x=1715008588; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U+jINRzKQ8ek5veBhc1V+WcM+rmOSm7v+UZN+AYLp0E=; b=A3N6db0lbtjwdmJuwq9ycoc7oKwxd67SAhGC/ZN9t+zMs9J48PDwwC4POAgK/eMOqo u/Ze41T9uygMaRHWndZZQHkcVsBYDicBd6i1WuUraVKqmZ4Hv8rsQxIuMwQ23baQJvpR AY+dkfxj9R4vq++hZtnOtAcqWRYN72Co2tWFs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714403788; x=1715008588; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U+jINRzKQ8ek5veBhc1V+WcM+rmOSm7v+UZN+AYLp0E=; b=SYDRtJex4kxGVU9VnoZ2fEH5Gl/PhStE+OeYEEPfvCU0+7TVK6Li8kCAx7j+r63HSD 3dwDKOqt2GqQ23mEs4xLC2tw2vp+QexzzvCmS/FCDYaJK7wwJrTk5ew7VFIRaUyNHQaD qU4mAhWTFyIL5VQ3xZsd3ToVfICuHPAA8nrbLpFbx5UftLr2JfpBubLHxBMINWnJZyiD +jrLjnqbSOdGcmhsDMS6NDDqiHS82vCyS5sTQsoi7k/gJxo9Illr8hrfL/6R39LbjUL6 ivh5y1zgVzHL1tRfDQD/d2SPCYmD8Sg3hIbP4/Le1ZgrBxcH1CJponB/CzbQDY31Anxl GoaA== X-Gm-Message-State: AOJu0Yws/8WCf5GlFAwO1QRvxGiXXwVJKLCbESOqfnjbX5Yn925fnb1J Fi50YNhmBqhy1KTJ2zq4wGDVISXjMLgcCW/yOHEZzfhQY70521tafx72QHtTOj8gImSBzy4pLOu v X-Google-Smtp-Source: AGHT+IE/C96C5lG5+P61Eon6C63GocYVL9KzxahT7A8hlbCisoZjEseQudsjd6yVoLdl4mDiR1tT8Q== X-Received: by 2002:a17:906:b798:b0:a4d:fcc9:905c with SMTP id dt24-20020a170906b79800b00a4dfcc9905cmr4938349ejb.20.1714403787775; Mon, 29 Apr 2024 08:16:27 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Xenia Ragiadakou , Sergiy Kibrik , George Dunlap , Andrei Semenov , Vaishali Thakkar Subject: [PATCH 1/5] x86/cpu-policy: Infrastructure for the AMD SVM and SEV leaves Date: Mon, 29 Apr 2024 16:16:21 +0100 Message-Id: <20240429151625.977884-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240429151625.977884-1-andrew.cooper3@citrix.com> References: <20240429151625.977884-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Allocate two new feature leaves, and extend cpu_policy with the non-feature fields too. The CPUID dependency between the SVM bit on the whole SVM leaf is intentionally deferred, to avoid transiently breaking nested virt. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné CC: Stefano Stabellini CC: Xenia Ragiadakou CC: Sergiy Kibrik CC: George Dunlap CC: Andrei Semenov CC: Vaishali Thakkar --- tools/libs/light/libxl_cpuid.c | 2 ++ tools/misc/xen-cpuid.c | 10 +++++++++ xen/arch/x86/cpu/common.c | 4 ++++ xen/include/public/arch-x86/cpufeatureset.h | 4 ++++ xen/include/xen/lib/x86/cpu-policy.h | 24 +++++++++++++++++++-- xen/lib/x86/cpuid.c | 4 ++++ 6 files changed, 46 insertions(+), 2 deletions(-) diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c index ce4f3c7095ba..c7a8b76f541d 100644 --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -342,6 +342,8 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *policy, const char* str) CPUID_ENTRY(0x00000007, 1, CPUID_REG_EDX), MSR_ENTRY(0x10a, CPUID_REG_EAX), MSR_ENTRY(0x10a, CPUID_REG_EDX), + CPUID_ENTRY(0x8000000a, NA, CPUID_REG_EDX), + CPUID_ENTRY(0x8000001f, NA, CPUID_REG_EAX), #undef MSR_ENTRY #undef CPUID_ENTRY }; diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 8893547bebce..ab09410a05d6 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -264,6 +264,14 @@ static const char *const str_m10Ah[32] = { }; +static const char *const str_eAd[32] = +{ +}; + +static const char *const str_e1Fa[32] = +{ +}; + static const struct { const char *name; const char *abbr; @@ -288,6 +296,8 @@ static const struct { { "CPUID 0x00000007:1.edx", "7d1", str_7d1 }, { "MSR_ARCH_CAPS.lo", "m10Al", str_m10Al }, { "MSR_ARCH_CAPS.hi", "m10Ah", str_m10Ah }, + { "CPUID 0x8000000a.edx", "eAd", str_eAd }, + { "CPUID 0x8000001f.eax", "e1Fa", str_e1Fa }, }; #define COL_ALIGN "24" diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 28d7f34c4dbe..25b11e6472b8 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -477,6 +477,10 @@ static void generic_identify(struct cpuinfo_x86 *c) c->x86_capability[FEATURESET_e7d] = cpuid_edx(0x80000007); if (c->extended_cpuid_level >= 0x80000008) c->x86_capability[FEATURESET_e8b] = cpuid_ebx(0x80000008); + if (c->extended_cpuid_level >= 0x8000000a) + c->x86_capability[FEATURESET_eAd] = cpuid_edx(0x8000000a); + if (c->extended_cpuid_level >= 0x8000001f) + c->x86_capability[FEATURESET_e1Fa] = cpuid_eax(0x8000001f); if (c->extended_cpuid_level >= 0x80000021) c->x86_capability[FEATURESET_e21a] = cpuid_eax(0x80000021); diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 53f13dec31f7..0f869214811e 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -357,6 +357,10 @@ XEN_CPUFEATURE(RFDS_CLEAR, 16*32+28) /*!A Register File(s) cleared by VE /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.edx, word 17 */ +/* AMD-defined CPU features, CPUID level 0x8000000a.edx, word 18 */ + +/* AMD-defined CPU features, CPUID level 0x8000001f.eax, word 19 */ + #endif /* XEN_CPUFEATURE */ /* Clean up from a default include. Close the enum (for C). */ diff --git a/xen/include/xen/lib/x86/cpu-policy.h b/xen/include/xen/lib/x86/cpu-policy.h index d5e447e9dc06..936e00e4da73 100644 --- a/xen/include/xen/lib/x86/cpu-policy.h +++ b/xen/include/xen/lib/x86/cpu-policy.h @@ -22,6 +22,8 @@ #define FEATURESET_7d1 15 /* 0x00000007:1.edx */ #define FEATURESET_m10Al 16 /* 0x0000010a.eax */ #define FEATURESET_m10Ah 17 /* 0x0000010a.edx */ +#define FEATURESET_eAd 18 /* 0x8000000a.edx */ +#define FEATURESET_e1Fa 19 /* 0x8000001f.eax */ struct cpuid_leaf { @@ -296,7 +298,16 @@ struct cpu_policy uint32_t /* d */:32; uint64_t :64, :64; /* Leaf 0x80000009. */ - uint64_t :64, :64; /* Leaf 0x8000000a - SVM rev and features. */ + + /* Leaf 0x8000000a - SVM rev and features. */ + uint8_t svm_rev, :8, :8, :8; + uint32_t /* b */ :32; + uint32_t nr_asids; + union { + uint32_t eAd; + struct { DECL_BITFIELD(eAd); }; + }; + uint64_t :64, :64; /* Leaf 0x8000000b. */ uint64_t :64, :64; /* Leaf 0x8000000c. */ uint64_t :64, :64; /* Leaf 0x8000000d. */ @@ -317,7 +328,16 @@ struct cpu_policy uint64_t :64, :64; /* Leaf 0x8000001c. */ uint64_t :64, :64; /* Leaf 0x8000001d - Cache properties. */ uint64_t :64, :64; /* Leaf 0x8000001e - Extd APIC/Core/Node IDs. */ - uint64_t :64, :64; /* Leaf 0x8000001f - AMD Secure Encryption. */ + + /* Leaf 0x8000001f - AMD Secure Encryption. */ + union { + uint32_t e1Fa; + struct { DECL_BITFIELD(e1Fa); }; + }; + uint32_t cbit:6, paddr_reduce:6, nr_vmpls:4, :16; + uint32_t nr_enc_guests; + uint32_t sev_min_asid; + uint64_t :64, :64; /* Leaf 0x80000020 - Platform QoS. */ /* Leaf 0x80000021 - Extended Feature 2 */ diff --git a/xen/lib/x86/cpuid.c b/xen/lib/x86/cpuid.c index eb7698dc7325..14deb01a6d0b 100644 --- a/xen/lib/x86/cpuid.c +++ b/xen/lib/x86/cpuid.c @@ -81,6 +81,8 @@ void x86_cpu_policy_to_featureset( fs[FEATURESET_7d1] = p->feat._7d1; fs[FEATURESET_m10Al] = p->arch_caps.lo; fs[FEATURESET_m10Ah] = p->arch_caps.hi; + fs[FEATURESET_eAd] = p->extd.eAd; + fs[FEATURESET_e1Fa] = p->extd.e1Fa; } void x86_cpu_featureset_to_policy( @@ -104,6 +106,8 @@ void x86_cpu_featureset_to_policy( p->feat._7d1 = fs[FEATURESET_7d1]; p->arch_caps.lo = fs[FEATURESET_m10Al]; p->arch_caps.hi = fs[FEATURESET_m10Ah]; + p->extd.eAd = fs[FEATURESET_eAd]; + p->extd.e1Fa = fs[FEATURESET_e1Fa]; } void x86_cpu_policy_recalc_synth(struct cpu_policy *p) From patchwork Mon Apr 29 15:16:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13647238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39124C19F53 for ; Mon, 29 Apr 2024 15:16:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.714186.1115272 (Exim 4.92) (envelope-from ) id 1s1Sk3-0006nC-EF; Mon, 29 Apr 2024 15:16:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 714186.1115272; Mon, 29 Apr 2024 15:16:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s1Sk3-0006n5-B6; Mon, 29 Apr 2024 15:16:31 +0000 Received: by outflank-mailman (input) for mailman id 714186; Mon, 29 Apr 2024 15:16:30 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s1Sk2-0006Yb-Bl for xen-devel@lists.xenproject.org; Mon, 29 Apr 2024 15:16:30 +0000 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [2a00:1450:4864:20::62b]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 74580315-063b-11ef-909b-e314d9c70b13; Mon, 29 Apr 2024 17:16:29 +0200 (CEST) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-a55ab922260so615803366b.3 for ; Mon, 29 Apr 2024 08:16:29 -0700 (PDT) Received: from andrewcoop.citrite.net (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id ah2-20020a1709069ac200b00a4e393b6349sm13898875ejc.5.2024.04.29.08.16.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 08:16:28 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 74580315-063b-11ef-909b-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1714403789; x=1715008589; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MI5h6UOov1WEGp6E29SV+XICdrE3ID4Y2ipNaivTcho=; b=e97P9c3+ERozSEXHyAfX0iRNeGuySjd/XoORSMxHzvr++GxKQe1wY9+bB4Ouqgbpii t4fua/QntdT/DyGm4QipFf5K1WkG4WaJiZGKflYMKdyxE2wOALS9KsFbsOTwZZdrfqo0 kRuEKJyJmXZtgkcWzLVkumK8sznBq1fbzRwFg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714403789; x=1715008589; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MI5h6UOov1WEGp6E29SV+XICdrE3ID4Y2ipNaivTcho=; b=CwO38OhZDME+QawE2KGBIpd9UVIfjRD1ZoeJBBRE4UNLBXKE361ONtVCVotXCxnku/ VBcJB42SbUXuQ8p910+s++7b7rcvALNQmDXFgmKDUXh3M4UsDWTldebtaHVjwkVjWHS6 X+6HlEMM0mJSunsP35mLkxsYjBedirjhR2zR69r3GmCqZtNlw2/MpGjQfbBM6HxzKoej iZeEDPJYxVDGnCEkgaabjaNnnwzIHi9XJxzz61qluA5oIivwK11EpdNLi659DvMmOZvR 4CtDZ02VMTLKCYunQw5Fp/GxSg1X9f5aIqDwtCh8TrcUcutwFay5ldbAgLapVmW6ZsS9 T4RA== X-Gm-Message-State: AOJu0YxYsOAxk0FUqeDi506FpuPMFuMAifJpV/aG2yq1fDw0KMXHz/qW r6c/euJqx25duKgvfr6T/uX/FrTFuqqK+l770atbQr0E3AgAPmGlxljzsftGHCmJQvloxru0eiG w X-Google-Smtp-Source: AGHT+IFp15N7bJoy1uj9VZVhqv262xx2DTCIl7aPyU0ozLfOJ9XP7as5n7JB5MZI1zMvOypBKRxu1A== X-Received: by 2002:a17:906:480f:b0:a52:3ff7:744d with SMTP id w15-20020a170906480f00b00a523ff7744dmr7425863ejq.4.1714403789013; Mon, 29 Apr 2024 08:16:29 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Xenia Ragiadakou , Sergiy Kibrik , George Dunlap , Andrei Semenov , Vaishali Thakkar Subject: [PATCH 2/5] x86/cpu-policy: Add SVM features already used by Xen Date: Mon, 29 Apr 2024 16:16:22 +0100 Message-Id: <20240429151625.977884-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240429151625.977884-1-andrew.cooper3@citrix.com> References: <20240429151625.977884-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 These will replace svm_feature_flags and the SVM_FEATURE_* constants over the next few changes. Take the opportunity to rationalise some names. Drop the opencoded "inherit from host" logic in calculate_hvm_max_policy() and use 'h'/'!' annotations. The logic needs to operate on fs, not the policy object, given its position within the function. Drop some trailing whitespace introduced when this block of code was last moved. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné CC: Stefano Stabellini CC: Xenia Ragiadakou CC: Sergiy Kibrik CC: George Dunlap CC: Andrei Semenov CC: Vaishali Thakkar --- tools/misc/xen-cpuid.c | 11 +++++++++++ xen/arch/x86/cpu-policy.c | 17 +++++------------ xen/include/public/arch-x86/cpufeatureset.h | 14 ++++++++++++++ xen/tools/gen-cpuid.py | 3 +++ 4 files changed, 33 insertions(+), 12 deletions(-) diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index ab09410a05d6..0d01b0e797f1 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -266,6 +266,17 @@ static const char *const str_m10Ah[32] = static const char *const str_eAd[32] = { + [ 0] = "npt", [ 1] = "v-lbr", + [ 2] = "svm-lock", [ 3] = "nrips", + [ 4] = "v-tsc-rate", [ 5] = "vmcb-cleanbits", + [ 6] = "flush-by-asid", [ 7] = "decode-assist", + + [10] = "pause-filter", + [12] = "pause-thresh", + /* 14 */ [15] = "v-loadsave", + [16] = "v-gif", + /* 18 */ [19] = "npt-sss", + [20] = "v-spec-ctrl", }; static const char *const str_e1Fa[32] = diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 4b6d96276399..da4401047e89 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -748,22 +747,16 @@ static void __init calculate_hvm_max_policy(void) if ( !cpu_has_vmx ) __clear_bit(X86_FEATURE_PKS, fs); - /* + /* * Make adjustments to possible (nested) virtualization features exposed * to the guest */ - if ( p->extd.svm ) + if ( test_bit(X86_FEATURE_SVM, fs) ) { - /* Clamp to implemented features which require hardware support. */ - p->extd.raw[0xa].d &= ((1u << SVM_FEATURE_NPT) | - (1u << SVM_FEATURE_LBRV) | - (1u << SVM_FEATURE_NRIPS) | - (1u << SVM_FEATURE_PAUSEFILTER) | - (1u << SVM_FEATURE_DECODEASSISTS)); - /* Enable features which are always emulated. */ - p->extd.raw[0xa].d |= (1u << SVM_FEATURE_VMCBCLEAN); + /* Xen always emulates cleanbits. */ + __set_bit(X86_FEATURE_VMCB_CLEANBITS, fs); } - + guest_common_max_feature_adjustments(fs); guest_common_feature_adjustments(fs); diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 0f869214811e..80d252a38c2d 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -358,6 +358,20 @@ XEN_CPUFEATURE(RFDS_CLEAR, 16*32+28) /*!A Register File(s) cleared by VE /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.edx, word 17 */ /* AMD-defined CPU features, CPUID level 0x8000000a.edx, word 18 */ +XEN_CPUFEATURE(NPT, 18*32+ 0) /*h Nested PageTables */ +XEN_CPUFEATURE(V_LBR, 18*32+ 1) /*h Virtualised LBR */ +XEN_CPUFEATURE(SVM_LOCK, 18*32+ 2) /* SVM locking MSR */ +XEN_CPUFEATURE(NRIPS, 18*32+ 3) /*h Next-RIP saved on VMExit */ +XEN_CPUFEATURE(V_TSC_RATE, 18*32+ 4) /* Virtualised TSC Ratio */ +XEN_CPUFEATURE(VMCB_CLEANBITS, 18*32+ 5) /*! VMCB Clean-bits */ +XEN_CPUFEATURE(FLUSH_BY_ASID, 18*32+ 6) /* TLB Flush by ASID */ +XEN_CPUFEATURE(DECODE_ASSIST, 18*32+ 7) /*h Decode assists */ +XEN_CPUFEATURE(PAUSE_FILTER, 18*32+10) /*h Pause filter */ +XEN_CPUFEATURE(PAUSE_THRESH, 18*32+12) /* Pause filter threshold */ +XEN_CPUFEATURE(V_LOADSAVE, 18*32+15) /* Virtualised VMLOAD/SAVE */ +XEN_CPUFEATURE(V_GIF, 18*32+16) /* Virtualised GIF */ +XEN_CPUFEATURE(NPT_SSS, 18*32+19) /* NPT Supervisor Shadow Stacks */ +XEN_CPUFEATURE(V_SPEC_CTRL, 18*32+20) /* Virtualised MSR_SPEC_CTRL */ /* AMD-defined CPU features, CPUID level 0x8000001f.eax, word 19 */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index bf3f9ec01e6e..f07b1f4cf905 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -280,6 +280,9 @@ def crunch_numbers(state): # standard 3DNow in the earlier K6 processors. _3DNOW: [_3DNOWEXT], + # The SVM bit enumerates the whole SVM leave. + SVM: list(range(NPT, NPT + 32)), + # This is just the dependency between AVX512 and AVX2 of XSTATE # feature flags. If want to use AVX512, AVX2 must be supported and # enabled. Certain later extensions, acting on 256-bit vectors of From patchwork Mon Apr 29 15:16:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13647235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF456C4345F for ; Mon, 29 Apr 2024 15:16:40 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.714188.1115292 (Exim 4.92) (envelope-from ) id 1s1Sk5-0007HB-UF; Mon, 29 Apr 2024 15:16:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 714188.1115292; Mon, 29 Apr 2024 15:16:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s1Sk5-0007H0-R3; Mon, 29 Apr 2024 15:16:33 +0000 Received: by outflank-mailman (input) for mailman id 714188; Mon, 29 Apr 2024 15:16:32 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s1Sk4-0006fc-Bd for xen-devel@lists.xenproject.org; Mon, 29 Apr 2024 15:16:32 +0000 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [2a00:1450:4864:20::136]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 74fb9fe8-063b-11ef-b4bb-af5377834399; Mon, 29 Apr 2024 17:16:30 +0200 (CEST) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-516ef30b16eso5113272e87.3 for ; Mon, 29 Apr 2024 08:16:30 -0700 (PDT) Received: from andrewcoop.citrite.net (default-46-102-197-194.interdsl.co.uk. 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No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné CC: Stefano Stabellini CC: Xenia Ragiadakou CC: Sergiy Kibrik CC: George Dunlap CC: Andrei Semenov CC: Vaishali Thakkar --- xen/arch/x86/include/asm/cpufeature.h | 3 +++ xen/arch/x86/spec_ctrl.c | 7 +------ 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index 9bc553681f4a..77cfd900cb56 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -217,6 +217,9 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_rfds_no boot_cpu_has(X86_FEATURE_RFDS_NO) #define cpu_has_rfds_clear boot_cpu_has(X86_FEATURE_RFDS_CLEAR) +/* CPUID level 0x8000000a.edx */ +#define cpu_has_v_spec_ctrl boot_cpu_has(X86_FEATURE_V_SPEC_CTRL) + /* Synthesized. */ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) #define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 40f6ae017010..0bda9d01def5 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -11,7 +11,6 @@ #include #include -#include #include #include #include @@ -1896,12 +1895,8 @@ void __init init_speculation_mitigations(void) * * No need for SCF_ist_sc_msr because Xen's value is restored * atomically WRT NMIs in the VMExit path. - * - * TODO: Adjust cpu_has_svm_spec_ctrl to be usable earlier on boot. */ - if ( opt_msr_sc_hvm && - (boot_cpu_data.extended_cpuid_level >= 0x8000000aU) && - (cpuid_edx(0x8000000aU) & (1u << SVM_FEATURE_SPEC_CTRL)) ) + if ( opt_msr_sc_hvm && cpu_has_v_spec_ctrl ) setup_force_cpu_cap(X86_FEATURE_SC_MSR_HVM); } From patchwork Mon Apr 29 15:16:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13647239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 568C6C25B10 for ; Mon, 29 Apr 2024 15:16:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.714189.1115298 (Exim 4.92) (envelope-from ) id 1s1Sk6-0007L6-Bl; Mon, 29 Apr 2024 15:16:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 714189.1115298; Mon, 29 Apr 2024 15:16:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s1Sk6-0007KB-51; Mon, 29 Apr 2024 15:16:34 +0000 Received: by outflank-mailman (input) for mailman id 714189; Mon, 29 Apr 2024 15:16:32 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s1Sk4-0006Yb-EK for xen-devel@lists.xenproject.org; Mon, 29 Apr 2024 15:16:32 +0000 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [2a00:1450:4864:20::631]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 75729faa-063b-11ef-909b-e314d9c70b13; Mon, 29 Apr 2024 17:16:31 +0200 (CEST) Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-a524ecaf215so581407966b.2 for ; Mon, 29 Apr 2024 08:16:31 -0700 (PDT) Received: from andrewcoop.citrite.net (default-46-102-197-194.interdsl.co.uk. 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It's entirely ad-hoc and not even everything printed here is used by Xen. It is available in `xen-cpuid` now. With (only) svm_load_segs_{,prefetch}() declared now in svm.h, only svm.c and domain.c which need the header. Clean up all others. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Vaishali Thakkar --- CC: Jan Beulich CC: Roger Pau Monné CC: Stefano Stabellini CC: Xenia Ragiadakou CC: Sergiy Kibrik CC: George Dunlap CC: Andrei Semenov CC: Vaishali Thakkar --- xen/arch/x86/hvm/svm/asid.c | 5 ++- xen/arch/x86/hvm/svm/emulate.c | 3 +- xen/arch/x86/hvm/svm/intr.c | 1 - xen/arch/x86/hvm/svm/nestedsvm.c | 14 ++++---- xen/arch/x86/hvm/svm/svm.c | 50 +++++++------------------- xen/arch/x86/hvm/svm/vmcb.c | 1 - xen/arch/x86/include/asm/cpufeature.h | 10 ++++++ xen/arch/x86/include/asm/hvm/svm/svm.h | 36 ------------------- 8 files changed, 31 insertions(+), 89 deletions(-) diff --git a/xen/arch/x86/hvm/svm/asid.c b/xen/arch/x86/hvm/svm/asid.c index 7977a8e86b53..6117a362d310 100644 --- a/xen/arch/x86/hvm/svm/asid.c +++ b/xen/arch/x86/hvm/svm/asid.c @@ -6,7 +6,6 @@ #include #include -#include #include "svm.h" @@ -39,7 +38,7 @@ void svm_asid_handle_vmrun(void) { vmcb_set_asid(vmcb, true); vmcb->tlb_control = - cpu_has_svm_flushbyasid ? TLB_CTRL_FLUSH_ASID : TLB_CTRL_FLUSH_ALL; + cpu_has_flush_by_asid ? TLB_CTRL_FLUSH_ASID : TLB_CTRL_FLUSH_ALL; return; } @@ -48,7 +47,7 @@ void svm_asid_handle_vmrun(void) vmcb->tlb_control = !need_flush ? TLB_CTRL_NO_FLUSH : - cpu_has_svm_flushbyasid ? TLB_CTRL_FLUSH_ASID : TLB_CTRL_FLUSH_ALL; + cpu_has_flush_by_asid ? TLB_CTRL_FLUSH_ASID : TLB_CTRL_FLUSH_ALL; } /* diff --git a/xen/arch/x86/hvm/svm/emulate.c b/xen/arch/x86/hvm/svm/emulate.c index 93ac1d3435f9..da6e21b2e270 100644 --- a/xen/arch/x86/hvm/svm/emulate.c +++ b/xen/arch/x86/hvm/svm/emulate.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include "svm.h" @@ -20,7 +19,7 @@ static unsigned long svm_nextrip_insn_length(struct vcpu *v) { struct vmcb_struct *vmcb = v->arch.hvm.svm.vmcb; - if ( !cpu_has_svm_nrips ) + if ( !cpu_has_nrips ) return 0; #ifndef NDEBUG diff --git a/xen/arch/x86/hvm/svm/intr.c b/xen/arch/x86/hvm/svm/intr.c index 4805c5567213..facd2894a2c6 100644 --- a/xen/arch/x86/hvm/svm/intr.c +++ b/xen/arch/x86/hvm/svm/intr.c @@ -17,7 +17,6 @@ #include #include #include -#include #include /* for nestedhvm_vcpu_in_guestmode */ #include #include diff --git a/xen/arch/x86/hvm/svm/nestedsvm.c b/xen/arch/x86/hvm/svm/nestedsvm.c index 35a2cbfd7d13..255af112661f 100644 --- a/xen/arch/x86/hvm/svm/nestedsvm.c +++ b/xen/arch/x86/hvm/svm/nestedsvm.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include @@ -1620,7 +1619,7 @@ void svm_nested_features_on_efer_update(struct vcpu *v) { if ( !vmcb->virt_ext.fields.vloadsave_enable && paging_mode_hap(v->domain) && - cpu_has_svm_vloadsave ) + cpu_has_v_loadsave ) { vmcb->virt_ext.fields.vloadsave_enable = 1; general2_intercepts = vmcb_get_general2_intercepts(vmcb); @@ -1629,8 +1628,7 @@ void svm_nested_features_on_efer_update(struct vcpu *v) vmcb_set_general2_intercepts(vmcb, general2_intercepts); } - if ( !vmcb->_vintr.fields.vgif_enable && - cpu_has_svm_vgif ) + if ( !vmcb->_vintr.fields.vgif_enable && cpu_has_v_gif ) { vintr = vmcb_get_vintr(vmcb); vintr.fields.vgif = svm->ns_gif; @@ -1675,8 +1673,8 @@ void __init start_nested_svm(struct hvm_function_table *hvm_function_table) */ hvm_function_table->caps.nested_virt = hvm_function_table->caps.hap && - cpu_has_svm_lbrv && - cpu_has_svm_nrips && - cpu_has_svm_flushbyasid && - cpu_has_svm_decode; + cpu_has_v_lbr && + cpu_has_nrips && + cpu_has_flush_by_asid && + cpu_has_decode_assist; } diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 4719fffae589..16eb875aab94 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1287,7 +1287,7 @@ static void cf_check svm_inject_event(const struct x86_event *event) * that hardware doesn't perform DPL checking on injection. */ if ( event->type == X86_EVENTTYPE_PRI_SW_EXCEPTION || - (!cpu_has_svm_nrips && (event->type >= X86_EVENTTYPE_SW_INTERRUPT)) ) + (!cpu_has_nrips && (event->type >= X86_EVENTTYPE_SW_INTERRUPT)) ) svm_emul_swint_injection(&_event); switch ( _event.vector | -(_event.type == X86_EVENTTYPE_SW_INTERRUPT) ) @@ -1341,7 +1341,7 @@ static void cf_check svm_inject_event(const struct x86_event *event) switch ( _event.type ) { case X86_EVENTTYPE_SW_INTERRUPT: /* int $n */ - if ( cpu_has_svm_nrips ) + if ( cpu_has_nrips ) vmcb->nextrip = regs->rip + _event.insn_len; else regs->rip += _event.insn_len; @@ -1355,7 +1355,7 @@ static void cf_check svm_inject_event(const struct x86_event *event) * semantics. */ regs->rip += _event.insn_len; - if ( cpu_has_svm_nrips ) + if ( cpu_has_nrips ) vmcb->nextrip = regs->rip; eventinj.type = X86_EVENTTYPE_HW_EXCEPTION; break; @@ -1365,7 +1365,7 @@ static void cf_check svm_inject_event(const struct x86_event *event) * Hardware special cases HW_EXCEPTION with vectors 3 and 4 as having * trap semantics, and will perform DPL checks. */ - if ( cpu_has_svm_nrips ) + if ( cpu_has_nrips ) vmcb->nextrip = regs->rip + _event.insn_len; else regs->rip += _event.insn_len; @@ -1982,7 +1982,7 @@ static int cf_check svm_msr_write_intercept( case MSR_IA32_DEBUGCTLMSR: vmcb_set_debugctlmsr(vmcb, msr_content); - if ( !msr_content || !cpu_has_svm_lbrv ) + if ( !msr_content || !cpu_has_v_lbr ) break; vmcb->virt_ext.fields.lbr_enable = 1; svm_disable_intercept_for_msr(v, MSR_IA32_DEBUGCTLMSR); @@ -2480,8 +2480,6 @@ static struct hvm_function_table __initdata_cf_clobber svm_function_table = { const struct hvm_function_table * __init start_svm(void) { - bool printed = false; - svm_host_osvw_reset(); if ( _svm_cpu_up(true) ) @@ -2493,38 +2491,14 @@ const struct hvm_function_table * __init start_svm(void) setup_vmcb_dump(); - if ( boot_cpu_data.extended_cpuid_level >= 0x8000000aU ) - svm_feature_flags = cpuid_edx(0x8000000aU); - - printk("SVM: Supported advanced features:\n"); - /* DecodeAssists fast paths assume nextrip is valid for fast rIP update. */ - if ( !cpu_has_svm_nrips ) - __clear_bit(SVM_FEATURE_DECODEASSISTS, &svm_feature_flags); + if ( !cpu_has_nrips ) + setup_clear_cpu_cap(X86_FEATURE_DECODE_ASSIST); if ( cpu_has_tsc_ratio ) svm_function_table.tsc_scaling.ratio_frac_bits = 32; -#define P(p,s) if ( p ) { printk(" - %s\n", s); printed = 1; } - P(cpu_has_svm_npt, "Nested Page Tables (NPT)"); - P(cpu_has_svm_lbrv, "Last Branch Record (LBR) Virtualisation"); - P(cpu_has_svm_nrips, "Next-RIP Saved on #VMEXIT"); - P(cpu_has_svm_cleanbits, "VMCB Clean Bits"); - P(cpu_has_svm_flushbyasid, "TLB flush by ASID"); - P(cpu_has_svm_decode, "DecodeAssists"); - P(cpu_has_svm_vloadsave, "Virtual VMLOAD/VMSAVE"); - P(cpu_has_svm_vgif, "Virtual GIF"); - P(cpu_has_pause_filter, "Pause-Intercept Filter"); - P(cpu_has_pause_thresh, "Pause-Intercept Filter Threshold"); - P(cpu_has_tsc_ratio, "TSC Rate MSR"); - P(cpu_has_svm_sss, "NPT Supervisor Shadow Stack"); - P(cpu_has_svm_spec_ctrl, "MSR_SPEC_CTRL virtualisation"); -#undef P - - if ( !printed ) - printk(" - none\n"); - - svm_function_table.caps.hap = cpu_has_svm_npt; + svm_function_table.caps.hap = cpu_has_npt; svm_function_table.caps.hap_superpage_2mb = true; svm_function_table.caps.hap_superpage_1gb = cpu_has_page1gb; @@ -2761,7 +2735,7 @@ void asmlinkage svm_vmexit_handler(void) regs->rax, regs->rbx, regs->rcx, regs->rdx, regs->rsi, regs->rdi); - if ( cpu_has_svm_decode ) + if ( cpu_has_decode_assist ) v->arch.hvm.svm.cached_insn_len = vmcb->guest_ins_len & 0xf; rc = paging_fault(va, regs); v->arch.hvm.svm.cached_insn_len = 0; @@ -2906,14 +2880,14 @@ void asmlinkage svm_vmexit_handler(void) case VMEXIT_CR0_READ ... VMEXIT_CR15_READ: case VMEXIT_CR0_WRITE ... VMEXIT_CR15_WRITE: - if ( cpu_has_svm_decode && vmcb->ei.mov_cr.mov_insn ) + if ( cpu_has_decode_assist && vmcb->ei.mov_cr.mov_insn ) svm_vmexit_do_cr_access(vmcb, regs); else if ( !hvm_emulate_one_insn(x86_insn_is_cr_access, "CR access") ) hvm_inject_hw_exception(X86_EXC_GP, 0); break; case VMEXIT_INVLPG: - if ( cpu_has_svm_decode ) + if ( cpu_has_decode_assist ) { svm_invlpg_intercept(vmcb->exitinfo1); __update_guest_eip(regs, vmcb->nextrip - vmcb->rip); @@ -2994,7 +2968,7 @@ void asmlinkage svm_vmexit_handler(void) break; case VMEXIT_NPF: - if ( cpu_has_svm_decode ) + if ( cpu_has_decode_assist ) v->arch.hvm.svm.cached_insn_len = vmcb->guest_ins_len & 0xf; rc = vmcb->ei.npf.ec & PFEC_page_present ? p2m_pt_handle_deferred_changes(vmcb->ei.npf.gpa) : 0; diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c index 4e1f61dbe038..4452ab1263d4 100644 --- a/xen/arch/x86/hvm/svm/vmcb.c +++ b/xen/arch/x86/hvm/svm/vmcb.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index 77cfd900cb56..b6fb8c24423c 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -218,6 +218,16 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_rfds_clear boot_cpu_has(X86_FEATURE_RFDS_CLEAR) /* CPUID level 0x8000000a.edx */ +#define cpu_has_npt boot_cpu_has(X86_FEATURE_NPT) +#define cpu_has_v_lbr boot_cpu_has(X86_FEATURE_V_LBR) +#define cpu_has_nrips boot_cpu_has(X86_FEATURE_NRIPS) +#define cpu_has_tsc_ratio boot_cpu_has(X86_FEATURE_V_TSC_RATE) +#define cpu_has_flush_by_asid boot_cpu_has(X86_FEATURE_FLUSH_BY_ASID) +#define cpu_has_decode_assist boot_cpu_has(X86_FEATURE_DECODE_ASSIST) +#define cpu_has_pause_filter boot_cpu_has(X86_FEATURE_PAUSE_FILTER) +#define cpu_has_pause_thresh boot_cpu_has(X86_FEATURE_PAUSE_THRESH) +#define cpu_has_v_loadsave boot_cpu_has(X86_FEATURE_V_LOADSAVE) +#define cpu_has_v_gif boot_cpu_has(X86_FEATURE_V_GIF) #define cpu_has_v_spec_ctrl boot_cpu_has(X86_FEATURE_V_SPEC_CTRL) /* Synthesized. */ diff --git a/xen/arch/x86/include/asm/hvm/svm/svm.h b/xen/arch/x86/include/asm/hvm/svm/svm.h index 4eeeb25da90c..06a951225e64 100644 --- a/xen/arch/x86/include/asm/hvm/svm/svm.h +++ b/xen/arch/x86/include/asm/hvm/svm/svm.h @@ -21,40 +21,4 @@ bool svm_load_segs(unsigned int ldt_ents, unsigned long ldt_base, unsigned long fs_base, unsigned long gs_base, unsigned long gs_shadow); -extern u32 svm_feature_flags; - -#define SVM_FEATURE_NPT 0 /* Nested page table support */ -#define SVM_FEATURE_LBRV 1 /* LBR virtualization support */ -#define SVM_FEATURE_SVML 2 /* SVM locking MSR support */ -#define SVM_FEATURE_NRIPS 3 /* Next RIP save on VMEXIT support */ -#define SVM_FEATURE_TSCRATEMSR 4 /* TSC ratio MSR support */ -#define SVM_FEATURE_VMCBCLEAN 5 /* VMCB clean bits support */ -#define SVM_FEATURE_FLUSHBYASID 6 /* TLB flush by ASID support */ -#define SVM_FEATURE_DECODEASSISTS 7 /* Decode assists support */ -#define SVM_FEATURE_PAUSEFILTER 10 /* Pause intercept filter support */ -#define SVM_FEATURE_PAUSETHRESH 12 /* Pause intercept filter support */ -#define SVM_FEATURE_VLOADSAVE 15 /* virtual vmload/vmsave */ -#define SVM_FEATURE_VGIF 16 /* Virtual GIF */ -#define SVM_FEATURE_SSS 19 /* NPT Supervisor Shadow Stacks */ -#define SVM_FEATURE_SPEC_CTRL 20 /* MSR_SPEC_CTRL virtualisation */ - -static inline bool cpu_has_svm_feature(unsigned int feat) -{ - return svm_feature_flags & (1u << feat); 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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id ah2-20020a1709069ac200b00a4e393b6349sm13898875ejc.5.2024.04.29.08.16.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 08:16:31 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7609761f-063b-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1714403792; x=1715008592; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CV04Tx+6NsZ8X0U2ufYfuFomh7VBRRmRmAKxgTh3wY4=; b=ul+veVfYxeRnBYKuGh62tNF+dlxekK+jLbnkK6MN773QU4zcOvQQ9Yqa4o9jMhxE5C IgTtHGNf6osYaGywVnEJqpAMG3wBqKxqhZAIARBqwZx4MK+KTKXjN50gwQ2zccOhx1pL vVWEmhedBsP7GQPJDF7kRVgwHDen4H8+ru69M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714403792; x=1715008592; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CV04Tx+6NsZ8X0U2ufYfuFomh7VBRRmRmAKxgTh3wY4=; b=ic+/xL0VlPR4qI3dJ+s2ttKmKREwSrnUjYdG6LCC0VgNDwrU7uWbNEnafpafvxduQg hXjuGIYzm6C2n9QIBBMP0taJqZHMlC4JSniKQSXbYa5u3cfTvOwMA5wrbgkVvbzljMyj 3kenc2Ae9nevkF8oeAZpLTwRLPWkjK6XVs8JEhuPHVCv/s7glK+4mOqHETKYEWh9CX0i JWJFxKhXuXFvO1wOGO6TT3wfejVeTaarwBSYp8MpxiQ1HI1Y6ETUBlFsBx3Q/wECHzmw 6911o08F5xcComTjvFPMLYZ797UbDn9Notd1cG14IGoWrLgvkHzZVKfObSTmURJveHXe r6qg== X-Gm-Message-State: AOJu0YwJeBDaldc4+TKYMUkni8+YszbHjkJNA4NvYbdHtmgDZGfjS2YH ncrU5FwiWwNdv4OtGySIIBwtadE4XLHnBTo0YvDJOzKKffikAG3/aeiYkrU8d2S3nMn0S4rQwew T X-Google-Smtp-Source: AGHT+IGO5TKFQYD+gTBIWeGVUOgzvtYEWbvErapDz4z7ZkjskrEyh/eDv+ptI2Mb53VrbReYfmobjw== X-Received: by 2002:a17:906:480f:b0:a58:8a33:1a39 with SMTP id w15-20020a170906480f00b00a588a331a39mr9853087ejq.3.1714403791795; Mon, 29 Apr 2024 08:16:31 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Xenia Ragiadakou , Sergiy Kibrik , George Dunlap , Andrei Semenov , Vaishali Thakkar Subject: [PATCH 5/5] x86/cpu-policy: Introduce some SEV features Date: Mon, 29 Apr 2024 16:16:25 +0100 Message-Id: <20240429151625.977884-6-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240429151625.977884-1-andrew.cooper3@citrix.com> References: <20240429151625.977884-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 For display purposes only right now. Signed-off-by: Andrew Cooper Reviewed-by: Vaishali Thakkar Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné CC: Stefano Stabellini CC: Xenia Ragiadakou CC: Sergiy Kibrik CC: George Dunlap CC: Andrei Semenov CC: Vaishali Thakkar This is only half the work to get SEV working nicely. The other half (rearranging __start_xen() so we can move the host policy collection earlier) is still a work-in-progress. --- tools/misc/xen-cpuid.c | 3 +++ xen/arch/x86/include/asm/cpufeature.h | 3 +++ xen/include/public/arch-x86/cpufeatureset.h | 4 ++++ xen/tools/gen-cpuid.py | 6 +++++- 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 0d01b0e797f1..1463e0429ba1 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -281,6 +281,9 @@ static const char *const str_eAd[32] = static const char *const str_e1Fa[32] = { + [ 0] = "sme", [ 1] = "sev", + /* 2 */ [ 3] = "sev-es", + [ 4] = "sev-snp", }; static const struct { diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index b6fb8c24423c..732f0d2bf758 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -230,6 +230,9 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_v_gif boot_cpu_has(X86_FEATURE_V_GIF) #define cpu_has_v_spec_ctrl boot_cpu_has(X86_FEATURE_V_SPEC_CTRL) +/* CPUID level 0x8000001f.eax */ +#define cpu_has_sev boot_cpu_has(X86_FEATURE_SEV) + /* Synthesized. */ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) #define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING) diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 80d252a38c2d..7ee0f2329151 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -374,6 +374,10 @@ XEN_CPUFEATURE(NPT_SSS, 18*32+19) /* NPT Supervisor Shadow Stacks * XEN_CPUFEATURE(V_SPEC_CTRL, 18*32+20) /* Virtualised MSR_SPEC_CTRL */ /* AMD-defined CPU features, CPUID level 0x8000001f.eax, word 19 */ +XEN_CPUFEATURE(SME, 19*32+ 0) /* Secure Memory Encryption */ +XEN_CPUFEATURE(SEV, 19*32+ 1) /* Secure Encryped VM */ +XEN_CPUFEATURE(SEV_ES, 19*32+ 3) /* SEV Encrypted State */ +XEN_CPUFEATURE(SEV_SNP, 19*32+ 4) /* SEV Secure Nested Paging */ #endif /* XEN_CPUFEATURE */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index f07b1f4cf905..bff4d9389ff6 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -281,7 +281,7 @@ def crunch_numbers(state): _3DNOW: [_3DNOWEXT], # The SVM bit enumerates the whole SVM leave. - SVM: list(range(NPT, NPT + 32)), + SVM: list(range(NPT, NPT + 32)) + [SEV], # This is just the dependency between AVX512 and AVX2 of XSTATE # feature flags. If want to use AVX512, AVX2 must be supported and @@ -341,6 +341,10 @@ def crunch_numbers(state): # The behaviour described by RRSBA depend on eIBRS being active. EIBRS: [RRSBA], + + SEV: [SEV_ES], + + SEV_ES: [SEV_SNP], } deep_features = tuple(sorted(deps.keys()))