From patchwork Fri May 3 11:14:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuklin Soo X-Patchwork-Id: 13652669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3FC6BC10F16 for ; Fri, 3 May 2024 11:15:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EPbkXvWPRBpQxPY4JmU4HIloqchyG3Qs9ltYcILo9Fk=; b=EnWORrIPLyLjJ8 mxN/PZr6a9qKD/w7Denv6lce7LW2hlljocmwmp2FNuBETWLDEcTZNRiFJnpVOA4aTa6Cz5Ov78rmX 8/EHpRvKMJIIk9aR0xQS5L39x4xIAXi6N05WZRVhuozNCDhrrjUPcajUFHzNV2jQRnMdRM6unOuUP hOmnT+AfCR9ydsKCsrI0H002arwNs+AIAWnbPYuXqXMgwhikkfxsNIybrIsRmtV/Y31y3MN8VLZlO 7M2NHloIF4hpF3kqTmHl3Q9WdsoUYnsE8roUwqtnDo+emGtjOyTDi/w+1S3P7zenmvGWTix+LFyvP m8zfMO65+aK2W+QnnTXA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qsW-0000000GCzt-2DIH; Fri, 03 May 2024 11:15:00 +0000 Received: from mail-sh0chn02on20708.outbound.protection.partner.outlook.cn ([2406:e500:4420:2::708] helo=CHN02-SH0-obe.outbound.protection.partner.outlook.cn) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qsS-0000000GCxl-1SaL for linux-riscv@lists.infradead.org; Fri, 03 May 2024 11:14:59 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hmOPBcQXYVeLmoG0Apl6abm4fcQ0C0N0uIOCtLaOA0Nu3F5M/7ERIO1Metxc/vMue9DIOesEqOu6VGkr1BVz4JaB20hkWibSrffIGELmba62lmQkGhYNmv1IqSYD2H/8TZWvue5Kq6iGVNus0B6olFLOYGBBHEl3QhqbEBaOWxtg/Rf6ax6w6XK/Op4K2rGi+YE+wstOzzDqkumOolCEE1eJ1D2SOtOZ56wwI1/2li9nd2+ghyRTPLhrU7BjfbZ7kJtqq+iebfCMiXDs9KeAPlJ+jl4SOHnC/vVGRjd5jyZvhhNyiUz4yCw+QBsvPitFPQrhSa91UKu1m5sCb589dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Jzw9HigR3la2YVeYR9LMvbl35xIpK1yS7Q9EmUSg5vY=; b=I9c5y2hswdS1MDak03ddjD7HBDNJrw2SK03dVZexdPGoCGvTu4yzwhZCjvEA59bDDez6G/6gKmbbqr+GBrZi2EGH9W7w48E5pCaLiU0GOWDiEkRfaAnWAOk6zgh2vkF+DlvnrQQodfvWSsWlQGd0cmLS+KUUcLcJwX51lQ3ebG9YsL0yqwPINgNEoKCAzejUmwH2gVCO3bOQaPtTQyYe5+NXMeMHQ5UnsOXvrHNQfXq95kOqsYOw4o05h+C7MbJmQNVFkhqEifqteSgpZMHIS4hv9iovIxr4bytzk6ELxV6znx9bDvX8jw9qBXH3tm2u/hnOEsWhJWCfA21HoH2kAw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) by ZQ0PR01MB1238.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:1b::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Fri, 3 May 2024 11:14:49 +0000 Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4]) by ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4%5]) with mapi id 15.20.7472.044; Fri, 3 May 2024 11:14:49 +0000 From: Alex Soo To: Linus Walleij , Bartosz Golaszewski , Hal Feng , Ley Foon Tan , Jianlong Huang , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alex Soo Subject: [RFC PATCH v3 1/7] dt-bindings: pinctrl: starfive: Add JH8100 pinctrl Date: Fri, 3 May 2024 19:14:30 +0800 Message-Id: <20240503111436.113089-2-yuklin.soo@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240503111436.113089-1-yuklin.soo@starfivetech.com> References: <20240503111436.113089-1-yuklin.soo@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0011.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::20) To ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1176:EE_|ZQ0PR01MB1238:EE_ X-MS-Office365-Filtering-Correlation-Id: 4bc3104f-2770-4983-d3ab-08dc6b623f8d X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5lSK7Nkln4jUzi+/6t4Zb9Arr+DjBLlBLLL6Npw46vtj2XYIydUQRkZwca5qndIma2RdOfNOWw3IFSEWE+HIxCHmmS6L8G+ihDSqpLMiuyLnaCD0S7FlVO4yFyVEON5WNMel8RZ1VWIx4CJ62zvkHcaqhxl2wkgcOYUdUGxdVZ5oZhAGh8K19IM0S8eTkjwHXHVn1vB06nlqxpPGTwgSJMazpUNsakrGPHZ1ADM8jrK9jvVYT/mfbZv/KyuJucU2jT26fVckSudrJgGTIp7w5WajNE5g2jBQmstnFIOIujTRv01WDrzdG56Mpjo3v0GyAJupl60ozwWywH4xC2uKqq3k3p/OR8fSOYh8RCBcsfltjohfVOIh9q26RRd/sKNqX4ql+emFePyBOltIrPCOh/+WgPUINiGiVrU3O1Q2e0rNJRCJf0cl1Lk/yLiNyLfs1kqOgFPOlhBqCb3QKAS3t9sX0rQ+n1AMOh/wnag0tlO67ftk7T2938PRXmCZQFxfYjSbNmXbDKWzKf+6p/PAin1Mor2ipqECH1MdzZ37eWRwNWB1UH345VqNInJjb//BgTlduYL4jXCVlFEj1a75zZiOO4MDAAE8u+AMVlR7aZfcw4BqQjgKgit/YmmMZPzMoEgD2Tb3Xgs5wNxySCgILw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230031)(52116005)(41320700004)(7416005)(366007)(1800799015)(38350700005)(921011);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SbcmLPMBSgl1htdXDq9Ddw1cMj2EQsuOKvIcHk205G94bQikc5vs+VVJ9tglID81pcc7hm7h9ka5s5TWZTtcdYLlQXHIeLyhDhxIzFoopdAwuP4aRB8sN91PQ0YJhWntYJsaHOhKeRQojJwKlt2tDTqZs73BVjYOXH3Jhwb0pRWQPeJbax2+TIJYjrFIeMUWHfAhvzMON+dv51pnZJQDKok6/NrM2SnuMxe7og3uRGvMjeZxySW8cd/lQT6Ly5zQdWzagwArfJfrdloF25+lGPBZHiVFLaet6zn2z1MnmyG4WC8pIotQzQRFJr2TZ2wplx21Q8gwuVARCiNq9kw+VwldRiSQ5JU7yOsMtAXpoZ8eZdXtW99sqb1n+rJKLTyjSqcWlPe8IvOX10y6nqtlFVyKjhXUCv5uAFqb4KN8JpLFE19drxNuVXAd4gJcJ6UXyjBcunWH1zYJ40sE7UZ6T7an06vWHJqJwrEvk4rLgUh2H524OtdagmhdRntX5UgRM0vSPznxzGOmqWEp8GhF8fVyp6vXRj0LntU8sYOj0nV9rtd1axGawcrbTQOs3Y0SLxlDQ5EZwa10ec7mhSIUl391ayM4aYByHy2yjxwFR0MH6NL9H4QAolqBgt56xvTknI5Mt5h3KGnwS5VPmLHITmztrBahztfTklR1VjOx06FNhUINGVIWV+eOnYa5hhcYAXD/dshNhIt8w+DQODEF/3d38D425ty/qj6zDX4Ywth0z47WheEtn3yhxG78JwT80BEF4fB3ZyUpvTgIrggKH3yTGTcw5abFRMx+5vauSryTyd9l48QzZ/2d6by0JvhYZJtsPAK3IaGw1t1D5c2aEQvl0NfxYW8F53bpmhBWh4p6/GL3KbbAJ3oNF1y6tF+TFZLP1SvsgDBFcZV5dagAKC4Shj+4L6jbStBCwQHv9etby8iqc3wGI4812cYpz7fI+kq/7VIbLoU9+sH+GhmFHZbTrWsgWKwuS5jTJD1tkmtS+SN1rDXT3wxJpcTal3tCdrYMcrpkShVQfeou8oQyCqJfyShnOkZS5SmkmavGZyDCErEf6ZboPuAf4i6WCyFLmRPRONCM4y9BjiRTuMAacBTrEdBC7v/hXDyzdxfhaZm8nApoQwewytWqHGDaD1BV3g6bdB5oiMggGb1O3sMnn86BVYdS+iQ57kXa5sO+36J3gUSdRIjGAbDQfTLUWoTYcTa3+imEm9d5q00K8HXpbZspRD+zb5+gUv+39RXGgzbsWo2t6Fdh7mPmYk3LeeV+iKPKk4VWnk0G7083icwwRSQf/bAZLYFk3pVSYB3DALFNIadHwJ+Yk+g0RflEu5lkERTK64mmNqXqb6cIau+s/hDrcNbwGxdulKn1c1EqE8nfgJQLwLnIyniC9hHrAh0N8PKEEuEsZBlDMV8fDtygyUhNGp6jOUPoGkY4arK7Khlk/xEpb3onwAfl2Xwh9LJ9IBzLYkIBA7H3zL5+9HXsIbbdH+lh/Zow8d2RrRwn7mAlapl1+nz+QqEWilHhJnzz4vxZzCOGUp61aYVtJVYlLiFMg/y/jyDszpMDwIPemBgpG+OSe3oLoBx5Ahq8fhVbAf0dPeuJFKAIvLklK1Bj9Q== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4bc3104f-2770-4983-d3ab-08dc6b623f8d X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 11:14:49.8998 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: vgSbwjZOzeqG3TdZvXvttGOs0hsPQAMhPPJkpD45fDuU3zzpCHVSqGFMCqk//jdPSG5RIQy28QpC9/SCeh+pk+4oBqPYbyUPMnAeddJgmxo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1238 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240503_041456_659789_127A7693 X-CRM114-Status: GOOD ( 20.05 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add documentation and header file for JH8100 pinctrl driver. Signed-off-by: Alex Soo --- .../pinctrl/starfive,jh8100-aon-pinctrl.yaml | 260 ++++++++++++++++++ .../starfive,jh8100-sys-east-pinctrl.yaml | 222 +++++++++++++++ .../starfive,jh8100-sys-gmac-pinctrl.yaml | 162 +++++++++++ .../starfive,jh8100-sys-west-pinctrl.yaml | 219 +++++++++++++++ .../pinctrl/starfive,jh8100-pinctrl.h | 13 + 5 files changed, 876 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh8100-aon-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-east-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-gmac-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-west-pinctrl.yaml create mode 100644 include/dt-bindings/pinctrl/starfive,jh8100-pinctrl.h diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-aon-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-aon-pinctrl.yaml new file mode 100644 index 000000000000..abd2a7570a54 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-aon-pinctrl.yaml @@ -0,0 +1,260 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh8100-aon-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 AON (always-on) Pin Controller + +description: | + Pinctrl bindings for JH8100 RISC-V SoC from StarFive Technology Ltd. + + The JH8100 SoC has 4 pinctrl domains - sys_east, sys_west, sys_gmac, and aon. + This document provides an overview of the "aon" pinctrl domain. + + The "aon" domain has a pin controller which provides + - I/O multiplexing for peripheral signals specific to this domain. + - GPIO pins which support external GPIO interrupts or external wake-up. + - syscon registers to configure device I/O reference voltage. + + In the AON Pin Controller, the pins named PAD_RGPIO0 to PAD_GPIO15 can be + multiplexed and have configurable bias, drive strength, schmitt trigger etc. + Only peripherals in the AON domain can have their I/O go through the 16 + "PAD_RGPIOs". This includes I2C, UART, watchdog, eMMC, SDIO0, XSPI etc. + + All these peripherals can be connected to any of the 16 PAD_RGPIOs in such a way + that any iopad can be set up to be controlled by any of the peripherals. + + The pin muxing is illustrated by the diagram below. + _____________ + | | + RGPIO0 --------------| |--- PAD_RGPIO0 + RGPIO1 --------------| AON I/O MUX |--- PAD_RGPIO1 + ... | | ... + I2C8 SDA interface --| |--- PAD_RGPIO15 + | | + ------------- + + The AON Pin Controller provides syscon registers to configure + + 1. reference voltage of + - eMMC I/O interface + supported voltage - 1.8V + - SDIO0 I/O interface + supported voltage - 3.3V, 1.8V + - PAD_RGPIO bank + - 16 PAD_RGPIOs (PAD_RGPIO0 to PAD_GPIO15) + - all devices attached to PAD_RGPIOs must use I/O voltage 3.3V. + - XSPI I/O interface + supported voltage level - 3.3V + + Regulator supplies the device voltage, and each device has a corresponding syscon + register bit [1:0] that must be configured to indicate the device voltage level. + + +--------+--------+-------------------+ + | Bit[1] | Bit[0] | Reference Voltage | + +--------+--------+-------------------+ + | 0 | 0 | 3.3 V | + +--------+--------+-------------------+ + | 0 | 1 | 2.5 V | + +--------+--------+-------------------+ + | 1 | x | 1.8 V | + +--------+--------+-------------------+ + + 2. reference voltage and slew rate of GMAC0 + + Voltage level on GMAC0 interface is dependent on the PHY that it is pairing with. The + supported voltage levels are 3.3V, 2.5V, and 1.8V. + + GMAC0 has 2 set of syscon registers - + + 2.1 PAD_VREF_GMAC0_syscon - bit [1:0] must be configured to indicate the voltage level on + GMAC0 interface. The default setting is 3.3V. + + +--------+--------+-----------------------------------+ + | Bit[1] | Bit[0] | GMAC0 Interface Reference Voltage | + +--------+--------+-----------------------------------+ + | 0 | 0 | 3.3V | + +--------+--------+-----------------------------------+ + | 0 | 1 | 2.5V | + +--------+--------+-----------------------------------+ + | 1 | x | 1.8V | + +--------+--------+-----------------------------------+ + + 2.2 PAD_GMAC0__syscon - each GMAC0 pad has a corresponding syscon bit [0] set + to 0 by default. When GMAC0 mode is RGMII and voltage level is 2.5V, the bit [0] must be + set to 1. + + +-------------+-----------------------+---------+ + | GMAC0 Mode | GMAC0 Voltage Level | Bit[0] | + +-------------+-----------------------+---------+ + | | 3.3V | 0 | + | |-----------------------+---------+ + | RGMII | 2.5V | 1 | + | |-----------------------+---------+ + | | 1.8V | 0 | + +-------------+-----------------------+---------+ + | | 3.3V | 0 | + | |-----------------------+---------+ + | RMII | 2.5V | 0 | + | |-----------------------+---------+ + | | 1.8V | 0 | + +-------------+-----------------------+---------+ + + the bit [2] can be used to configure GMAC0 signal slew rate, + + +--------+-----------+ + | Bit[2] | Slew Rate | + +--------+-----------+ + | 0 | Fast | + +--------+-----------+ + | 1 | Slow | + +--------+-----------+ + + Under any circumstances, the syscon register's reference voltage setting must not be + lower than the actual device voltage, otherwise, the device I/O pads will get damaged. + + Follow the guidelines below when configure reference voltage - + + To increase the device voltage, set bit [1:0] to the new operating state first before + raising the actual voltage to the higher operating point. + + To decrease the device voltage, hold bit [1:0] to the current operating state until + the actual voltage has stabilized at the lower operating point before changing the + setting. + + Alternatively, a device voltage change can always be initiated by first setting syscon + register bit [1:0] = 0, the safe 3.3V startup condition, before changing the device + voltage. Then once the actual voltage is changed and has stabilized at the new operating + point, bit [1:0] can be reset as appropriate. + +maintainers: + - Alex Soo + +properties: + compatible: + - items: + - const: starfive,jh8100-aon-pinctrl + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + wakeup-gpios: + maxItems: 1 + description: GPIO pin to be used for waking up the system from sleep mode. + + wakeup-source: + maxItems: 1 + description: to indicate pinctrl has wakeup capability. + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + unevaluatedProperties: false + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings or function select. + The GPIOMUX and PINMUX macros are used to configure the + I/O multiplexing and function selection respectively. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow (half frequency) + 1: fast + +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_aon: pinctrl@1f300000 { + compatible = "starfive,jh8100-aon-pinctrl", "syscon", "simple-mfd"; + reg = <0x0 0x1f300000 0x0 0x10000>; + resets = <&aoncrg 0>; + interrupts = <160>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aon 0 0 16>; + + i2c7_pins: i2c7-grp { + i2c7-scl-pins { + pinmux = <0x23265409>; + bias-pull-up; + input-enable; + }; + + i2c7-sda-pins { + pinmux = <0x2427580a>; + bias-pull-up; + input-enable; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-east-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-east-pinctrl.yaml new file mode 100644 index 000000000000..6ad518e9bee2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-east-pinctrl.yaml @@ -0,0 +1,222 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh8100-sys-east-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 SYS_EAST Pin Controller + +description: | + Pinctrl bindings for JH8100 RISC-V SoC from StarFive Technology Ltd. + + The JH8100 SoC has 4 pinctrl domains - sys_east, sys_west, sys_gmac, and aon. + This document provides an overview of the "sys_east" pinctrl domain. + + The "sys_east" domain has a pin controller which provides + - I/O multiplexing for peripheral signals specific to this domain. + - function selection for GPIO pads. + - GPIO interrupt handling. + - syscon for device voltage reference. + + In the SYS_EAST Pin Controller, the pins named PAD_GPIO0_E to PAD_GPIO47_E can + be multiplexed and have configurable bias, drive strength, schmitt trigger etc. + Only peripherals in the SYS_EAST domain can have their I/O go through the 48 + "PAD_GPIOs". This includes CANs, I2Cs, I2Ss, SPIs, UARTs, PWMs, SMBUS0, SDIO1 etc. + + All these peripherals can be connected to any of the 48 PAD_GPIOs in such a way + that any iopad can be set up to be controlled by any of the peripherals. + + The pin muxing is illustrated by the diagram below. + __________________ + | | + GPIO0 ----------------------| |--- PAD_GPIO0_E + GPIO1 ----------------------| SYS_EAST I/O MUX |--- PAD_GPIO1_E + GPIO2 ----------------------| |--- PAD_GPIO2_E + ... | | ... + I2C0 Clock interface -------| |--- PAD_GPIO9_E + I2C0 Data interface -------| |--- PAD_GPIO10_E + ... | | ... + UART0 transmit interface ---| |--- PAD_GPIO20_E + UART0 receive interface ----| |--- PAD_GPIO21_E + ... | | ... + GPIO47 ---------------------| |--- PAD_GPIO47_E + | | + ------------------ + + Alternatively, the "PAD_GPIOs" can be multiplexed to other peripherals through + function selection. Each iopad has a maximum of up to 3 functions - 0, 1, and 2. + Function 0 is the default function or peripheral signal of an iopad. + The function 1 and function 2 are other optional functions or peripheral signals + available to an iopad. The function selection can be carried out by writing the + function number to the iopad function select register. + + The "sys_east" domain has 4 PAD_GPIO banks - + E0 - 16 PAD_GPIOs (PAD_GPIO0_E to PAD_GPIO15_E) + E1 - 16 PAD_GPIOs (PAD_GPIO16_E to PAD_GPIO31_E) + E2 - 8 PAD_GPIOs (PAD_GPIO32_E to PAD_GPIO39_E) + E3 - 8 PAD_GPIOs (PAD_GPIO40_E to PAD_GPIO47_E) + + Each PAD_GPIO bank can be set to a voltage level 3.3V or 1.8V. All devices attached + to the PAD_GPIOs must use the same I/O voltage level as the bank voltage setting. + This allows user to select different I/O voltages for their devices. For instance, + the UART have 3.3V/1.8V requirement, the UART devices that use 1.8V are attached + to a PAD_GPIO bank which is configured to 1.8V. + + Regulators supply voltages to the PAD_GPIO banks, and each PAD_GPIO bank has a corresponding + syscon bit [1:0] that must be configured to indicate its voltage level. The default setting + is 3.3V. + + +--------+--------+-------------------+ + | Bit[1] | Bit[0] | Reference Voltage | + +--------+--------+-------------------+ + | 0 | 0 | 3.3 V | + +--------+--------+-------------------+ + | 1 | x | 1.8 V | + +--------+--------+-------------------+ + + Under any circumstances, the syscon register's reference voltage setting must not be + lower than the actual device voltage, otherwise, the device I/O pads will get damaged. + + Follow the guidelines below when configure reference voltage - + + To increase the device voltage, set bit [1:0] to the new operating state first before + raising the actual voltage to the higher operating point. + + To decrease the device voltage, hold bit [1:0] to the current operating state until + the actual voltage has stabilized at the lower operating point before changing the + setting. + + Alternatively, a device voltage change can always be initiated by first setting syscon + register bit [1:0] = 0, the safe 3.3V startup condition, before changing the device + voltage. Then once the actual voltage is changed and has stabilized at the new operating + point, bit [1:0] can be reset as appropriate. + +maintainers: + - Alex Soo + +properties: + compatible: + - items: + - const: starfive,jh8100-sys-pinctrl-east + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + unevaluatedProperties: false + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings or function select. + The GPIOMUX and PINMUX macros are used to configure the + I/O multiplexing and function selection respectively. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow (half frequency) + 1: fast + +required: + - compatible + - reg + - clocks + - resets + - interrupts + - interrupt-controller + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_east: pinctrl@122d0000 { + compatible = "starfive,jh8100-sys-pinctrl-east", "syscon", "simple-mfd"; + reg = <0x0 0x122d0000 0x0 0x10000>; + clocks = <&syscrg_ne 153>; + resets = <&syscrg_ne 48>; + interrupts = <182>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_east 0 0 48>; + + smbus0_pins: smbus0-grp { + smbus0-scl-pins { + pinmux = <0x1122480b>; + bias-pull-up; + input-enable; + }; + + smbus0-sda-pins { + pinmux = <0x12234c0c>; + bias-pull-up; + input-enable; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-gmac-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-gmac-pinctrl.yaml new file mode 100644 index 000000000000..567ff0d9fd6c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-gmac-pinctrl.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh8100-sys-gmac-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 SYS_GMAC Pin Controller + +description: | + Pinctrl bindings for JH8100 RISC-V SoC from StarFive Technology Ltd. + + The JH8100 SoC has 4 pinctrl domains - sys_east, sys_west, sys_gmac, and aon. + This document provides an overview of the "sys_gmac" pinctrl domain. + + The "sys_gmac" domain has a pin-controller which provides syscon registers to + configure device reference voltage and slew rate. + + The SYS_GMAC Pin Controller does not have any PAD_GPIOs, therefore, it does not + support the GPIO pad I/O Multiplexing and interrupt handling. + + The SYS_GMAC Pin Controller provides syscon registers to configure + + 1. reference voltage of SDIO1 + + The supported voltage levels are 3.3V and 1.8V + + The bit [1:0] must be configured to indicate the SDIO1 voltage level. + + +--------+--------+--------------------------+ + | Bit[1] | Bit[0] | SDIO1 Reference Voltage | + +--------+--------+--------------------------+ + | 0 | 0 | 3.3 V | + +--------+--------+--------------------------+ + | 1 | 0 | 1.8 V | + +--------+--------+--------------------------+ + + 2. reference voltage and slew rate of GMAC1 + + Voltage level on GMAC1 interface is dependent on the PHY that it is pairing with. The + supported voltage levels are 3.3V, 2.5V, and 1.8V. + + GMAC1 has 2 set of syscon registers - + + 2.1 PAD_VREF_GMAC1_syscon - bit [1:0] must be configured to indicate the voltage level on + GMAC1 interface. The default setting is 3.3V. + + +--------+--------+-----------------------------------+ + | Bit[1] | Bit[0] | GMAC1 Interface Reference Voltage | + +--------+--------+-----------------------------------+ + | 0 | 0 | 3.3V | + +--------+--------+-----------------------------------+ + | 0 | 1 | 2.5V | + +--------+--------+-----------------------------------+ + | 1 | x | 1.8V | + +--------+--------+-----------------------------------+ + + 2.2 PAD_GMAC1__syscon - each GMAC1 pad has a corresponding syscon bit [0] set + to 0 by default. When GMAC1 mode is RGMII and voltage level is 2.5V, the bit [0] must be + set to 1. + + +-------------+-----------------------+---------+ + | GMAC1 Mode | GMAC1 Voltage Level | Bit[0] | + +-------------+-----------------------+---------+ + | | 3.3V | 0 | + | |-----------------------+---------+ + | RGMII | 2.5V | 1 | + | |-----------------------+---------+ + | | 1.8V | 0 | + +-------------+-----------------------+---------+ + | | 3.3V | 0 | + | |-----------------------+---------+ + | RMII | 2.5V | 0 | + | |-----------------------+---------+ + | | 1.8V | 0 | + +-------------+-----------------------+---------+ + + the bit [2] can be used to configure the GMAC1 signal slew rate, + + +--------+-----------+ + | Bit[2] | Slew Rate | + +--------+-----------+ + | 0 | Fast | + +--------+-----------+ + | 1 | Slow | + +--------+-----------+ + + Under any circumstances, the syscon register's reference voltage setting must not be + lower than the actual voltage, otherwise, the device I/O pads will get damaged. + + Follow the guidelines below when configure reference voltage - + + To increase the device voltage, set bit [1:0] to the new operating state first before + raising the actual voltage to the higher operating point. + + To decrease the device voltage, hold bit [1:0] to the current operating state until + the actual voltage has stabilized at the lower operating point before changing the + setting. + + Alternatively, a device voltage change can always be initiated by first setting syscon + register bit [1:0] = 0, the safe 3.3V startup condition, before changing the device + voltage. Then once the actual voltage is changed and has stabilized at the new operating + point, bit [1:0] can be reset as appropriate. + +maintainers: + - Alex Soo + +properties: + compatible: + - items: + - const: starfive,jh8100-sys-pinctrl-gmac + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_gmac: pinctrl@12770000 { + compatible = "starfive,jh8100-sys-pinctrl-gmac", "syscon", "simple-mfd"; + reg = <0x0 0x12770000 0x0 0x10000>; + clocks = <&gmac_sdio_crg 16>; + resets = <&gmac_sdio_crg 3>; + }; + + }; diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-west-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-west-pinctrl.yaml new file mode 100644 index 000000000000..ecff5656ecc3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-west-pinctrl.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh8100-sys-west-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 SYS_WEST Pin Controller + +description: | + Pinctrl bindings for JH8100 RISC-V SoC from StarFive Technology Ltd. + + The JH8100 SoC has 4 pinctrl domains - sys_east, sys_west, sys_gmac, and aon. + This document provides an overview of the "sys_west" pinctrl domain. + + The "sys_west" domain has a pin-controller which provides + - I/O multiplexing for peripheral signals specific to this domain. + - function selection for GPIO pads. + - GPIO interrupt handling. + - syscon for device voltage reference. + + In the SYS_WEST Pin Controller, the pins named PAD_GPIO0_W to PAD_GPIO15_W can + be multiplexed and have configurable bias, drive strength, schmitt trigger etc. + Only peripherals in the SYS_WEST domain can have their I/O go through the 16 + "PAD_GPIOs". This includes I2Cs, HD_AUDIO, HIFI4, SPIs, UARTs, SMBUS1 etc. + + All these peripherals can be connected to any of the 16 PAD_GPIOs in such a way + that any iopad can be set up to be controlled by any of the peripherals. + + The pin muxing is illustrated by the diagram below. + __________________ + | | + GPIO0 ----------------------| |--- PAD_GPIO0_W + GPIO1 ----------------------| SYS_WEST I/O MUX |--- PAD_GPIO1_W + GPIO2 ----------------------| |--- PAD_GPIO2_W + ... | | ... + HIFI4 JTAG TDO interface ---| |--- PAD_GPIO10_W + HIFI4 JTAG TDI interface ---| |--- PAD_GPIO11_W + SMBUS1 Data interface -----| |--- PAD_GPIO12_W + SMBUS1 Clock interface -----| |--- PAD_GPIO13_W + ... | | ... + GPIO14 ---------------------| |--- PAD_GPIO14_W + GPIO15 ---------------------| |--- PAD_GPIO15_W + | | + ------------------ + + Alternatively, the "PAD_GPIOs" can be multiplexed to other peripherals through + function selection. Each iopad has a maximum of up to 3 functions - 0, 1, and 2. + Function 0 is the default function or peripheral signal of an iopad. + The function 1 and function 2 are other optional functions or peripheral signals + available to an iopad. The function selection can be carried out by writing the + function number to the iopad function select register. + + The "sys_west" domain has one PAD_GPIO bank - + W0 - 16 PAD_GPIOs (PAD_GPIO0_W to PAD_GPIO15_W) + + The PAD_GPIO bank can be set to voltage level 3.3V or 1.8V. All devices attached + to the PAD_GPIOs must use the same I/O voltage level as the bank voltage setting. + This allows user to select different I/O voltages for their devices. For instance, + the UART have 3.3V/1.8V requirement, the UART devices that use 1.8V are attached + to a PAD_GPIO bank which is configured to 1.8V. + + Regulator supplies voltage to the PAD_GPIO bank, and the PAD_GPIO bank has a + corresponding syscon bit [1:0] that must be configured to indicate its voltage + level. The default voltage setting of each PAD_GPIO bank is 3.3V. + + +--------+--------+-------------------+ + | Bit[1] | Bit[0] | Reference Voltage | + +--------+--------+-------------------+ + | 0 | 0 | 3.3 V | + +--------+--------+-------------------+ + | 1 | x | 1.8 V | + +--------+--------+-------------------+ + + Under any circumstances, the syscon register's reference voltage setting must not be + lower than the actual device voltage, otherwise, the device I/O pads will get damaged. + + Follow the guidelines below when configure reference voltage - + + To increase the device voltage, set bit [1:0] to the new operating state first before + raising the actual voltage to the higher operating point. + + To decrease the device voltage, hold bit [1:0] to the current operating state until + the actual voltage has stabilized at the lower operating point before changing the + setting. + + Alternatively, a device voltage change can always be initiated by first setting syscon + register bit [1:0] = 0, the safe 3.3V startup condition, before changing the device + voltage. Then once the actual voltage is changed and has stabilized at the new operating + point, bit [1:0] can be reset as appropriate. + +maintainers: + - Alex Soo + +properties: + compatible: + - items: + - const: starfive,jh8100-sys-pinctrl-west + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + unevaluatedProperties: false + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings or function select. + The GPIOMUX and PINMUX macros are used to configure the + I/O multiplexing and function selection respectively. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow (half frequency) + 1: fast + +required: + - compatible + - reg + - clocks + - resets + - interrupts + - interrupt-controller + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_west: pinctrl@123e0000 { + compatible = "starfive,jh8100-sys-pinctrl-west", "syscon", "simple-mfd"; + reg = <0x0 0x123e0000 0x0 0x10000>; + clocks = <&syscrg_nw 6>; + resets = <&syscrg_nw 1>; + interrupts = <183>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_west 0 0 16>; + + smbus1_pins: smbus1-grp { + smbus1-scl-pins { + pinmux = <0x1014300d>; + bias-pull-up; + input-enable; + }; + + smbus1-sda-pins { + pinmux = <0x1115340c>; + bias-pull-up; + input-enable; + }; + }; + }; + }; diff --git a/include/dt-bindings/pinctrl/starfive,jh8100-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jh8100-pinctrl.h new file mode 100644 index 000000000000..153ba950c062 --- /dev/null +++ b/include/dt-bindings/pinctrl/starfive,jh8100-pinctrl.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH8100_H__ +#define __DT_BINDINGS_PINCTRL_STARFIVE_JH8100_H__ + +/* Pad Slew Rates */ +#define PAD_SLEW_RATE_FAST 1 +#define PAD_SLEW_RATE_SLOW 0 + +#endif From patchwork Fri May 3 11:14:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuklin Soo X-Patchwork-Id: 13652671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3CA5C4345F for ; Fri, 3 May 2024 11:15:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YGlBbvyfxrJlOWidc8D5dEISh2DNzoDgvn96ZcsUPh4=; b=30tIJ198ZBLm+s nwayf203FVZToOGTWOLOzmaBWbCisBiCx/PqDqE/XMWgNB9mFqSpvkDe1U2t4yHA2oBmWWuwfuUox ukKPwBra0fjs/EQBpeR07i58fTiSNTAGkhzz/+NgECu/Hquq1cnJnzrYnw8lqNZ4SUAnQW3W0bj+P hpRscvLNUpy3ycP7i5uvAXxRvInZtqjVqhhmh65kafS4FW2INHZDtK6neyhOu1UTrcDI6nkN6ZON0 dL17RXz5KDYXBOQuYbv5/QKAhNrcoAcBwZjN73imnSL/fRSh0cAjYc5IOHjUcgXYikPCfW2TNW+gv XcVKtGjgC9ZsznU6Aolw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qsa-0000000GD18-1bjh; Fri, 03 May 2024 11:15:04 +0000 Received: from mail-sh0chn02on20708.outbound.protection.partner.outlook.cn ([2406:e500:4420:2::708] helo=CHN02-SH0-obe.outbound.protection.partner.outlook.cn) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qsV-0000000GCxl-3RcV for linux-riscv@lists.infradead.org; Fri, 03 May 2024 11:15:03 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TaMA5oLHEn8AUhqn6l8zgjHPvL4HEWDbOMh5qKICfKhusMbCxGLFAEBczGXWLkg3GJZw5SF6W/g85m7KBnFHy6ffxF8uvDOw2hRtVACfRqQxnD211GOQuTUSfOjIjuesdOH7XkZCrT16lFRKZMrz3r8tPOOHtuvqBfSfJVIdwNEcl1Li2TiYkfnmJmUJLG1FpT54dUC97UdgI4Q7lkEWiMg2ccx7/xjRmae5I5WuwUXEFmIM1YPxayWmyj2bzuYSDfJFSUp6GuBCyRKUvHoVpNTtityRRCQPOv3+v6YCfZB17Tu5G3DMxODiECbcx1KQesd3FouCghxpTg5F1kb+JQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vDdCVsDCb/VueupHtMM8rDUA+vzCW0UtHbAaJOIf6VY=; b=QKS2v848HrJRAXM6Fm4nrfG1lQo6/4ptYCzITUfQMGoDw3+G+x90oti8K9p/K6ezldCI9E4mLQe1cj4sXRXCrdkMTQlAtOuWkWFbGIaMsCU+Ke4ARC+6xdB2/NatxRl6c8+N3NU0J6/uoqtWPx8XDaci5nPSzS5AG7w3DkEffyW+HzpBGiFu8vWcIoerLO+sITjmYn3SwiT29TGNNkXHxPHX4OG3JC+cV3YpSkbAPzKoWVYS/NE4sNKI5fy9jCH8fPTaMyUX3tinFAhxZaMN03AAipf6Y3VhQSgEVX+dbdMlEI0LNgKbKsIMlUaxbLjcbW0w1UOmamrzYBmQaSbNgw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) by ZQ0PR01MB1238.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:1b::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Fri, 3 May 2024 11:14:53 +0000 Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4]) by ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4%5]) with mapi id 15.20.7472.044; Fri, 3 May 2024 11:14:53 +0000 From: Alex Soo To: Linus Walleij , Bartosz Golaszewski , Hal Feng , Ley Foon Tan , Jianlong Huang , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alex Soo Subject: [RFC PATCH v3 2/7] pinctrl: starfive: jh8100: add main driver and sys_east domain sub-driver Date: Fri, 3 May 2024 19:14:31 +0800 Message-Id: <20240503111436.113089-3-yuklin.soo@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240503111436.113089-1-yuklin.soo@starfivetech.com> References: <20240503111436.113089-1-yuklin.soo@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0011.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::20) To ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1176:EE_|ZQ0PR01MB1238:EE_ X-MS-Office365-Filtering-Correlation-Id: aec45f71-2f6e-47c9-e0e7-08dc6b624166 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lgFP9C2Znwsl25f2b7eY18mYHoT5G/TB8r/u8ixqFZpqHEfQ11fAG0W31sL+E6Y22EsctfJmlcCqHIcbWqqjpfMryo/6X/jLsHFD0NzKvNI/Roue5Z307IwjHEvq8C984vWLkN0r3QNgAGZGKmaFgrlWm1YEKZs46cwhibKzR1w/63Ba6dbkpOtBIN1UrlpfHy9awSeQW/kL1iYeDNsq6UCBPo+e+4zXdnnC00Nq5bCH3kUDAvVINEyoOczEU6TRwvtDDeQBpBUZxWw0DSzExpdQ5lnRVnrHaWOkdp854q32ujwQPtJTEYkqQmCDzEy1cMKbVuzR2yq3sH6Psm8fKDOqpBPEJOpTkf1hjdBwEv6UuCd6CCK7sO4pQgWrIovFZo6e/CbYHY6W27scm2YUv5LAot4B+0onbHNUXz4nc+IpM/lv5GBF5uuStLVMLe/hvi5skx93FIPkdF++7lWfLxmub8YFH5MhVfp/6pplXoMHkSf8RCXzfl+WzqESdf1Ngc7SMWeKqLqSsVjSjEz1eP1EvkoOdud6RZIhsqEMvFG6DrRH6lTuVexbEN4n1VhCwCsPLGdlT64ZwCrp/FF3sC173RPM5ByjyJnNlm0Lzg2dIr38khIYHPZbqNpNFGnv+y/dO1sFyFAujc3pEU0MsQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230031)(52116005)(41320700004)(7416005)(366007)(1800799015)(38350700005)(921011);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4S9Zby6l9uw05im4PUnOkZ8iBGN7rY3SaWlQjFJl1BFw6ZpCoLoCKy8XOhoAj+tX3r0youbR+J/ZTz60+m7fbZ/2Mb+M7jDvneLWjxyv9eZRvKZ3fsxv8ncjBn9rmBPb9biUiD44LbHQ9fdWmvNir7YNqPTFTl0TCmYEQgtfb9Xe7FYcsmEdWLI7ZkGfs6ndE5xpKxv1i1+KuBQy3Pl89n5Wg6UAY6e2EGuTG3oJZMXylBKWb/63capXcW85taX2itvWjHT02eysinsLxTqOlTNzjwbiQqcHoOXaw+D+ShqJOz9gMF27Zqms92ZEyt9l3WGcAUiOYQJjfPsjvFUjl+rOFCVppLxgE6ODrpyNvqtJj86CPP4sgQvHHyLpADsWoYhxxV5uLBqt3MEY4+T+OaNEpVb7kg5XfrjAjVTawaAGBWftLWeZ3AhdrNcpTHcNg21ma61nk7wr7MZjUFzwR7aSBpDt88PCvm/OVxUxNciPaCGvdiOXvPLaFlU5TSpQ2K1q0vppE04+6Fze4nCdYYTVKBdPeZGOSip/TFw/RO8iGzDnhch6dWcfhC0TWEryKCYdTXbYrYkZYZM3puTac+QRh7HJhIc8t0QAOKKj1CJ3uIIn8xtaVbXqFq1UanG+w0yUerLRin2LCmbT5qDIj0ApMzMQ/ZxI2/Dy/zoTnjPipaiHQMkA4SXdoIwsNXORh7atduDf8p3M3ePFxSBjFt+xbdIFDx3pNBwgF/yluNRxkaEmNoSjB0Cx1J7CvK7SnT2q4U8el0FI5VbJoRdO4QplCrliuG7mG7C+8eQWcmfsABL0NaJkW0sZ15mPJtdpju17fv/rwUwTWaTo5BApyBmW6BFkg5WaqOoxl7t1MD8GTjpkJ5ZC+MzMJXm8SOOsb/03M+L2YC/CYMcBgM2vDr5/kB1Yhqpk5HW4nNQhVVp8OO1UNc4WHqMszKUEQT2uz6C9178iz5DVJH1u/WC9L2R8OoCsUj7sFa4+2ZTVk/n0gG4Mxn7DY5BzmvoOdCgsiTdoymKwMc5Q34h0oVV5YVWgogyP3sVO6Tzd8IsIgvLDSQ3z8P50giNrD96wiNSWLpFC4ZFcHnDQDyS1lU0+s6r7l8Aq2seZeLSb2dRDQN4+KROH68G99FRAyE6iDoJR/bxLCsqcTEfLjrFfs53HqGFfz17TB018cKARjClNX+nluIa4AwbENiBAAEbVk4hlqPUxWs6uL0M9iMmhoLoh4SQjWCKr5gXePhXLPLe6EcTnPrQbMXhP+5s/XRqVUfNV971WAhMHvnHoOfGQaIq9R2lqihTQcX/3kZBgucwAJmNjEdcrGRHlmldIjpeh/PiuOgh5S48whjuSqTdF6LF+3O+4w532MZOts5CTj36E+k2f63ggF3xRQ4jh280r5ThSZyGJoU9+uLCkOzh5AWKR7vjCh9UhQBVw6CpTi2y1nRGFrQSOfP3DJLiQCYJJ8sHpSh7YyUWKfPY4uVpcNTTcljoddUXqNimioWbmpBKvbBSDjWDpgAVYuHhvKKX9UqyEHRxNIjRpdX7pOznZb7gFqJSlRvYRYEOu8TsOo+nPX6vpzyLZs7uleIajnPPqDcAQwNqQ6KLedUGY8E1oOECIFA== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: aec45f71-2f6e-47c9-e0e7-08dc6b624166 X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 11:14:52.9978 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Sf1WVLkKkXrhic+QPIm0xKjcIrXiN7yZ7Vuwne0FB8F2qfueqAgkTSUbCCAlOGBxDZJHwXi1jq6A5ZSVmBKyaMuENimHPRiRTo+7ra+uOhU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1238 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240503_041500_090588_757C9E64 X-CRM114-Status: GOOD ( 20.93 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add Starfive JH8100 SoC pinctrl main driver to provide the common APIs that are used by the sub-drivers of pinctrl domains: - sys_east, - sys_west, - sys_gmac, - aon (always-on) to implement the following tasks: - applies pin multiplexing, function selection, and pin configuration for devices during system initialization or change of pinctrl state due to power management. - read or set pin configuration from user space. Also, add the sys_east domain sub-driver since it requires at least one domain sub-driver to run the probe function in the main driver to enable the basic pinctrl functionalities on the system. Signed-off-by: Alex Soo --- drivers/pinctrl/starfive/Kconfig | 21 + drivers/pinctrl/starfive/Makefile | 3 + .../pinctrl-starfive-jh8100-sys-east.c | 220 ++++ .../starfive/pinctrl-starfive-jh8100.c | 1094 +++++++++++++++++ .../starfive/pinctrl-starfive-jh8100.h | 111 ++ 5 files changed, 1449 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-east.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 8192ac2087fc..afcbf9d4dc8d 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -49,3 +49,24 @@ config PINCTRL_STARFIVE_JH7110_AON This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JH8100 + bool + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIOLIB_IRQCHIP + select OF_GPIO + +config PINCTRL_STARFIVE_JH8100_SYS_EAST + tristate "StarFive JH8100 SoC System IOMUX-East pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + depends on OF + select PINCTRL_STARFIVE_JH8100 + default ARCH_STARFIVE + help + Say yes here to support system iomux-east pin control on the StarFive JH8100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index ee0d32d085cb..45698c502b48 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -5,3 +5,6 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-starfive-jh7110.o obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o + +obj-$(CONFIG_PINCTRL_STARFIVE_JH8100) += pinctrl-starfive-jh8100.o +obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_EAST) += pinctrl-starfive-jh8100-sys-east.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-east.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-east.c new file mode 100644 index 000000000000..45ade4d68d66 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-east.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC sys east controller + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include +#include +#include +#include + +#include + +#include "pinctrl-starfive-jh8100.h" + +#define JH8100_SYS_E_GC_BASE 16 + +/* registers */ +#define JH8100_SYS_E_DOEN 0x000 +#define JH8100_SYS_E_DOUT 0x030 +#define JH8100_SYS_E_GPI 0x060 +#define JH8100_SYS_E_GPIOIN 0x0f4 + +#define JH8100_SYS_E_GPIOEN 0x0b8 +#define JH8100_SYS_E_GPIOIS0 0x0bc +#define JH8100_SYS_E_GPIOIS1 0x0c0 +#define JH8100_SYS_E_GPIOIC0 0x0c4 +#define JH8100_SYS_E_GPIOIC1 0x0c8 +#define JH8100_SYS_E_GPIOIBE0 0x0cc +#define JH8100_SYS_E_GPIOIBE1 0x0d0 +#define JH8100_SYS_E_GPIOIEV0 0x0d4 +#define JH8100_SYS_E_GPIOIEV1 0x0d8 +#define JH8100_SYS_E_GPIOIE0 0x0dc +#define JH8100_SYS_E_GPIOIE1 0x0e0 +#define JH8100_SYS_E_GPIORIS0 0x0e4 +#define JH8100_SYS_E_GPIORIS1 0x0e8 +#define JH8100_SYS_E_GPIOMIS0 0x0ec +#define JH8100_SYS_E_GPIOMIS1 0x0f0 + +static const struct pinctrl_pin_desc jh8100_sys_e_pins[] = { + PINCTRL_PIN(0, "SYS_E_GPIO0"), + PINCTRL_PIN(1, "SYS_E_GPIO1"), + PINCTRL_PIN(2, "SYS_E_GPIO2"), + PINCTRL_PIN(3, "SYS_E_GPIO3"), + PINCTRL_PIN(4, "SYS_E_GPIO4"), + PINCTRL_PIN(5, "SYS_E_GPIO5"), + PINCTRL_PIN(6, "SYS_E_GPIO6"), + PINCTRL_PIN(7, "SYS_E_GPIO7"), + PINCTRL_PIN(8, "SYS_E_GPIO8"), + PINCTRL_PIN(9, "SYS_E_GPIO9"), + PINCTRL_PIN(10, "SYS_E_GPIO10"), + PINCTRL_PIN(11, "SYS_E_GPIO11"), + PINCTRL_PIN(12, "SYS_E_GPIO12"), + PINCTRL_PIN(13, "SYS_E_GPIO13"), + PINCTRL_PIN(14, "SYS_E_GPIO14"), + PINCTRL_PIN(15, "SYS_E_GPIO15"), + PINCTRL_PIN(16, "SYS_E_GPIO16"), + PINCTRL_PIN(17, "SYS_E_GPIO17"), + PINCTRL_PIN(18, "SYS_E_GPIO18"), + PINCTRL_PIN(19, "SYS_E_GPIO19"), + PINCTRL_PIN(20, "SYS_E_GPIO20"), + PINCTRL_PIN(21, "SYS_E_GPIO21"), + PINCTRL_PIN(22, "SYS_E_GPIO22"), + PINCTRL_PIN(23, "SYS_E_GPIO23"), + PINCTRL_PIN(24, "SYS_E_GPIO24"), + PINCTRL_PIN(25, "SYS_E_GPIO25"), + PINCTRL_PIN(26, "SYS_E_GPIO26"), + PINCTRL_PIN(27, "SYS_E_GPIO27"), + PINCTRL_PIN(28, "SYS_E_GPIO28"), + PINCTRL_PIN(29, "SYS_E_GPIO29"), + PINCTRL_PIN(30, "SYS_E_GPIO30"), + PINCTRL_PIN(31, "SYS_E_GPIO31"), + PINCTRL_PIN(32, "SYS_E_GPIO32"), + PINCTRL_PIN(33, "SYS_E_GPIO33"), + PINCTRL_PIN(34, "SYS_E_GPIO34"), + PINCTRL_PIN(35, "SYS_E_GPIO35"), + PINCTRL_PIN(36, "SYS_E_GPIO36"), + PINCTRL_PIN(37, "SYS_E_GPIO37"), + PINCTRL_PIN(38, "SYS_E_GPIO38"), + PINCTRL_PIN(39, "SYS_E_GPIO39"), + PINCTRL_PIN(40, "SYS_E_GPIO40"), + PINCTRL_PIN(41, "SYS_E_GPIO41"), + PINCTRL_PIN(42, "SYS_E_GPIO42"), + PINCTRL_PIN(43, "SYS_E_GPIO43"), + PINCTRL_PIN(44, "SYS_E_GPIO44"), + PINCTRL_PIN(45, "SYS_E_GPIO45"), + PINCTRL_PIN(46, "SYS_E_GPIO46"), + PINCTRL_PIN(47, "SYS_E_GPIO47"), +}; + +static const struct jh8100_gpio_func_sel + jh8100_sys_e_func_sel[ARRAY_SIZE(jh8100_sys_e_pins)] = { + [20] = { 0x1d4, 0, 2 }, + [21] = { 0x1d4, 2, 2 }, + [22] = { 0x1d4, 4, 2 }, + [23] = { 0x1d4, 6, 2 }, + [24] = { 0x1d4, 8, 2 }, + [25] = { 0x1d4, 10, 2 }, + [26] = { 0x1d4, 12, 2 }, + [27] = { 0x1d4, 14, 2 }, + [28] = { 0x1d4, 16, 2 }, + [29] = { 0x1d4, 18, 2 }, + [30] = { 0x1d4, 20, 2 }, + [31] = { 0x1d4, 22, 2 }, + [32] = { 0x1d4, 24, 2 }, + [33] = { 0x1d4, 26, 2 }, + [34] = { 0x1d4, 28, 2 }, + [35] = { 0x1d4, 30, 2 }, + + [36] = { 0x1d8, 0, 2 }, + [37] = { 0x1d8, 2, 2 }, + [38] = { 0x1d8, 4, 2 }, + [39] = { 0x1d8, 6, 2 }, + [40] = { 0x1d8, 8, 2 }, + [41] = { 0x1d8, 10, 2 }, + [42] = { 0x1d8, 12, 2 }, + [43] = { 0x1d8, 14, 2 }, + [44] = { 0x1d8, 16, 2 }, + [45] = { 0x1d8, 18, 2 }, + [46] = { 0x1d8, 20, 2 }, + [47] = { 0x1d8, 22, 2 }, +}; + +#ifdef CONFIG_PM_SLEEP +static int jh8100_sys_e_pinctrl_suspend(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + sfp->jh8100_sys_east_regs[i] = readl_relaxed(sfp->base + (i * 4)); + + return pinctrl_force_sleep(sfp->pctl); +} + +static int jh8100_sys_e_pinctrl_resume(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + writel_relaxed(sfp->jh8100_sys_east_regs[i], sfp->base + (i * 4)); + + return pinctrl_force_default(sfp->pctl); +} +#endif + +static SIMPLE_DEV_PM_OPS(jh8100_sys_e_pinctrl_dev_pm_ops, + jh8100_sys_e_pinctrl_suspend, + jh8100_sys_e_pinctrl_resume); + +static const struct jh8100_gpio_irq_reg jh8100_sys_e_irq_reg = { + .is_reg_base = JH8100_SYS_E_GPIOIS0, + .ic_reg_base = JH8100_SYS_E_GPIOIC0, + .ic1_reg_base = JH8100_SYS_E_GPIOIC1, + .ibe_reg_base = JH8100_SYS_E_GPIOIBE0, + .iev_reg_base = JH8100_SYS_E_GPIOIEV0, + .ie_reg_base = JH8100_SYS_E_GPIOIE0, + .ris_reg_base = JH8100_SYS_E_GPIORIS0, + .mis_reg_base = JH8100_SYS_E_GPIOMIS0, + .mis1_reg_base = JH8100_SYS_E_GPIOMIS1, + .ien_reg_base = JH8100_SYS_E_GPIOEN, +}; + +static const struct jh8100_pinctrl_domain_info jh8100_sys_e_pinctrl_info = { + .pins = jh8100_sys_e_pins, + .npins = ARRAY_SIZE(jh8100_sys_e_pins), + .ngpios = JH8100_SYS_E_NGPIO, + .gc_base = JH8100_SYS_E_GC_BASE, + .name = JH8100_SYS_E_DOMAIN_NAME, + .nregs = JH8100_SYS_E_REG_NUM, + .dout_reg_base = JH8100_SYS_E_DOUT, + .dout_mask = GENMASK(6, 0), + .doen_reg_base = JH8100_SYS_E_DOEN, + .doen_mask = GENMASK(5, 0), + .gpi_reg_base = JH8100_SYS_E_GPI, + .gpi_mask = GENMASK(5, 0), + .gpioin_reg_base = JH8100_SYS_E_GPIOIN, + .func_sel = jh8100_sys_e_func_sel, + .irq_reg = &jh8100_sys_e_irq_reg, + .mis_pin_num = 32, + .mis1_pin_num = 16, +}; + +static const struct of_device_id jh8100_sys_e_pinctrl_of_match[] = { + { + .compatible = "starfive,jh8100-sys-pinctrl-east", + .data = &jh8100_sys_e_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh8100_sys_e_pinctrl_of_match); + +static struct platform_driver jh8100_sys_e_pinctrl_driver = { + .probe = jh8100_pinctrl_probe, + .driver = { + .name = "starfive-jh8100-sys-pinctrl-east", +#ifdef CONFIG_PM_SLEEP + .pm = &jh8100_sys_e_pinctrl_dev_pm_ops, +#endif + .of_match_table = jh8100_sys_e_pinctrl_of_match, + }, +}; +module_platform_driver(jh8100_sys_e_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JH8100 SoC sys east controller"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c new file mode 100644 index 000000000000..4b68463ff5a5 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c @@ -0,0 +1,1094 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "pinctrl-starfive-jh8100.h" + +/* pad control bits */ +#define JH8100_PADCFG_POS BIT(7) +#define JH8100_PADCFG_SMT BIT(6) +#define JH8100_PADCFG_SLEW BIT(5) +#define JH8100_PADCFG_PD BIT(4) +#define JH8100_PADCFG_PU BIT(3) +#define JH8100_PADCFG_BIAS_MASK (JH8100_PADCFG_PD | JH8100_PADCFG_PU) +#define JH8100_PADCFG_DS_MASK GENMASK(2, 1) +#define JH8100_PADCFG_DS_2MA (0U << 1) +#define JH8100_PADCFG_DS_4MA (1U << 1) +#define JH8100_PADCFG_DS_8MA (2U << 1) +#define JH8100_PADCFG_DS_12MA (3U << 1) +#define JH8100_PADCFG_IE BIT(0) + +/* + * The packed pinmux values from the device tree look like this: + * + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din | dout | doen | function | pin | + */ +static unsigned int jh8100_pinmux_din(u32 v) +{ + return (v & GENMASK(31, 24)) >> 24; +} + +static u32 jh8100_pinmux_dout(u32 v) +{ + return (v & GENMASK(23, 16)) >> 16; +} + +static u32 jh8100_pinmux_doen(u32 v) +{ + return (v & GENMASK(15, 10)) >> 10; +} + +static u32 jh8100_pinmux_function(u32 v) +{ + return (v & GENMASK(9, 8)) >> 8; +} + +static unsigned int jh8100_pinmux_pin(u32 v) +{ + return v & GENMASK(7, 0); +} + +static struct jh8100_pinctrl *jh8100_from_irq_data(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + return container_of(gc, struct jh8100_pinctrl, gc); +} + +struct jh8100_pinctrl *jh8100_from_irq_desc(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + + return container_of(gc, struct jh8100_pinctrl, gc); +} +EXPORT_SYMBOL_GPL(jh8100_from_irq_desc); + +#ifdef CONFIG_DEBUG_FS +static void jh8100_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct jh8100_pinctrl_domain_info *info = sfp->info; + + seq_printf(s, "%s", dev_name(pctldev->dev)); + + if (pin < sfp->gc.ngpio) { + unsigned int offset = 4 * (pin / 4); + unsigned int shift = 8 * (pin % 4); + u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset); + u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); + u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset); + + dout = (dout >> shift) & info->dout_mask; + doen = (doen >> shift) & info->doen_mask; + gpi = ((gpi >> shift) - 2) & info->gpi_mask; + + seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi); + } +} +#else +#define jh8100_pin_dbg_show NULL +#endif + +static int jh8100_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = sfp->gc.parent; + struct device_node *child; + struct pinctrl_map *map; + const char **pgnames; + const char *grpname; + int ngroups; + int nmaps; + int ret; + + ngroups = 0; + for_each_child_of_node(np, child) + ngroups += 1; + nmaps = 2 * ngroups; + + pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL); + if (!pgnames) + return -ENOMEM; + + map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + nmaps = 0; + ngroups = 0; + mutex_lock(&sfp->mutex); + for_each_child_of_node(np, child) { + int npins = of_property_count_u32_elems(child, "pinmux"); + int *pins; + u32 *pinmux; + int i; + + if (npins < 1) { + dev_err(dev, + "invalid pinctrl group %pOFn.%pOFn: pinmux not set\n", + np, child); + ret = -EINVAL; + goto put_child; + } + + grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child); + if (!grpname) { + ret = -ENOMEM; + goto put_child; + } + + pgnames[ngroups++] = grpname; + + pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) { + ret = -ENOMEM; + goto put_child; + } + + pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL); + if (!pinmux) { + ret = -ENOMEM; + goto put_child; + } + + ret = of_property_read_u32_array(child, "pinmux", pinmux, npins); + if (ret) + goto put_child; + + for (i = 0; i < npins; i++) + pins[i] = jh8100_pinmux_pin(pinmux[i]); + + map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; + map[nmaps].data.mux.function = np->name; + map[nmaps].data.mux.group = grpname; + nmaps += 1; + + ret = pinctrl_generic_add_group(pctldev, grpname, + pins, npins, pinmux); + if (ret < 0) { + dev_err(dev, "error adding group %s: %d\n", grpname, ret); + goto put_child; + } + + ret = pinconf_generic_parse_dt_config(child, pctldev, + &map[nmaps].data.configs.configs, + &map[nmaps].data.configs.num_configs); + if (ret) { + dev_err(dev, "error parsing pin config of group %s: %d\n", + grpname, ret); + goto put_child; + } + + /* don't create a map if there are no pinconf settings */ + if (map[nmaps].data.configs.num_configs == 0) + continue; + + map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + map[nmaps].data.configs.group_or_pin = grpname; + nmaps += 1; + } + + ret = pinmux_generic_add_function(pctldev, np->name, + pgnames, ngroups, NULL); + if (ret < 0) { + dev_err(dev, "error adding function %s: %d\n", np->name, ret); + goto free_map; + } + mutex_unlock(&sfp->mutex); + + *maps = map; + *num_maps = nmaps; + return 0; + +put_child: + of_node_put(child); +free_map: + pinctrl_utils_free_map(pctldev, map, nmaps); + mutex_unlock(&sfp->mutex); + return ret; +} + +static const struct pinctrl_ops jh8100_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .pin_dbg_show = jh8100_pin_dbg_show, + .dt_node_to_map = jh8100_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; + +void jh8100_set_gpiomux(struct jh8100_pinctrl *sfp, unsigned int pin, + unsigned int din, u32 dout, u32 doen) +{ + const struct jh8100_pinctrl_domain_info *info = sfp->info; + + unsigned int offset = 4 * (pin / 4); + unsigned int shift = 8 * (pin % 4); + u32 dout_mask = info->dout_mask << shift; + u32 done_mask = info->doen_mask << shift; + u32 ival, imask; + u32 tmp; + void __iomem *reg_dout; + void __iomem *reg_doen; + void __iomem *reg_din; + unsigned long flags; + + reg_dout = sfp->base + info->dout_reg_base + offset; + reg_doen = sfp->base + info->doen_reg_base + offset; + dout <<= shift; + doen <<= shift; + if (din != 255) { + unsigned int ioffset = 4 * (din / 4); + unsigned int ishift = 8 * (din % 4); + + reg_din = sfp->base + info->gpi_reg_base + ioffset; + ival = (pin + 2) << ishift; + imask = info->gpi_mask << ishift; + } else { + reg_din = NULL; + } + + raw_spin_lock_irqsave(&sfp->lock, flags); + dout |= readl_relaxed(reg_dout) & ~dout_mask; + writel_relaxed(dout, reg_dout); + doen |= readl_relaxed(reg_doen) & ~done_mask; + writel_relaxed(doen, reg_doen); + if (reg_din) { + tmp = readl_relaxed(reg_din) & ~imask; + writel_relaxed(tmp, reg_din); + ival |= readl_relaxed(reg_din) & ~imask; + writel_relaxed(ival, reg_din); + } + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void jh8100_set_function(struct jh8100_pinctrl *sfp, + unsigned int pin, u32 func) +{ + const struct jh8100_gpio_func_sel *fs = &sfp->info->func_sel[pin]; + unsigned long flags; + void __iomem *reg; + u32 mask; + + if (!fs->offset) + return; + + if (func > fs->max) + return; + + reg = sfp->base + fs->offset; + func = func << fs->shift; + mask = 0x3U << fs->shift; + + raw_spin_lock_irqsave(&sfp->lock, flags); + func |= readl_relaxed(reg) & ~mask; + writel_relaxed(func, reg); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static int jh8100_set_one_pin_mux(struct jh8100_pinctrl *sfp, + unsigned int pin, + unsigned int din, u32 dout, + u32 doen, u32 func) +{ + if (pin < sfp->gc.ngpio && func == 0) + jh8100_set_gpiomux(sfp, pin, din, dout, doen); + + if (!strcmp(sfp->info->name, JH8100_SYS_E_DOMAIN_NAME) && + pin < sfp->gc.ngpio && func == 1) + jh8100_set_function(sfp, pin, func); + + return 0; +} + +static int jh8100_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *group; + const u32 *pinmux; + unsigned int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + pinmux = group->data; + + for (i = 0; i < group->grp.npins; i++) { + u32 v = pinmux[i]; + + jh8100_set_one_pin_mux(sfp, + jh8100_pinmux_pin(v), + jh8100_pinmux_din(v), + jh8100_pinmux_dout(v), + jh8100_pinmux_doen(v), + jh8100_pinmux_function(v)); + } + + return 0; +} + +static const struct pinmux_ops jh8100_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = jh8100_set_mux, + .strict = true, +}; + +static const u8 jh8100_drive_strength_mA[4] = { 2, 4, 8, 12 }; + +static u32 jh8100_padcfg_ds_to_mA(u32 padcfg) +{ + return jh8100_drive_strength_mA[(padcfg >> 1) & 3U]; +} + +static u32 jh8100_padcfg_ds_to_uA(u32 padcfg) +{ + return jh8100_drive_strength_mA[(padcfg >> 1) & 3U] * 1000; +} + +static u32 jh8100_padcfg_ds_from_mA(u32 v) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(jh8100_drive_strength_mA); i++) { + if (v <= jh8100_drive_strength_mA[i]) + break; + } + return i << 1; +} + +static u32 jh8100_padcfg_ds_from_uA(u32 v) +{ + /* Convert from uA to mA */ + v /= 1000; + + return jh8100_padcfg_ds_from_mA(v); +} + +static int jh8100_get_padcfg_base(struct jh8100_pinctrl *sfp, + unsigned int pin) +{ + if (!strcmp(sfp->info->name, JH8100_SYS_E_DOMAIN_NAME)) { + if (pin < JH8100_SYS_E_NGPIO) + return JH8100_SYS_E_GPO_PDA_00_47_CFG; + } + + return -ENXIO; +} + +static void jh8100_padcfg_rmw(struct jh8100_pinctrl *sfp, + unsigned int pin, u32 mask, u32 value) +{ + void __iomem *reg; + unsigned long flags; + int padcfg_base; + + padcfg_base = jh8100_get_padcfg_base(sfp, pin); + if (padcfg_base < 0) + return; + + reg = sfp->base + padcfg_base + 4 * pin; + value &= mask; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value |= readl_relaxed(reg) & ~mask; + writel_relaxed(value, reg); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static int jh8100_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + int param = pinconf_to_config_param(*config); + u32 padcfg, arg; + bool enabled; + int padcfg_base; + + padcfg_base = jh8100_get_padcfg_base(sfp, pin); + if (padcfg_base < 0) + return 0; + + padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin); + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + enabled = !(padcfg & JH8100_PADCFG_BIAS_MASK); + arg = 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + enabled = padcfg & JH8100_PADCFG_PD; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + enabled = padcfg & JH8100_PADCFG_PU; + arg = 1; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + enabled = true; + arg = jh8100_padcfg_ds_to_mA(padcfg); + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + enabled = true; + arg = jh8100_padcfg_ds_to_uA(padcfg); + break; + case PIN_CONFIG_INPUT_ENABLE: + enabled = padcfg & JH8100_PADCFG_IE; + arg = enabled; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + enabled = padcfg & JH8100_PADCFG_SMT; + arg = enabled; + break; + case PIN_CONFIG_SLEW_RATE: + enabled = true; + arg = !!(padcfg & JH8100_PADCFG_SLEW); + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return enabled ? 0 : -EINVAL; +} + +static int jh8100_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int gpio, unsigned long *config, + unsigned int num_configs) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + u32 param; + u32 arg; + u32 value; + u32 mask; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(config[i]); + arg = pinconf_to_config_argument(config[i]); + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask = JH8100_PADCFG_BIAS_MASK; + value = 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg == 0) + return -ENOTSUPP; + mask = JH8100_PADCFG_BIAS_MASK; + value = JH8100_PADCFG_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg == 0) + return -ENOTSUPP; + mask = JH8100_PADCFG_BIAS_MASK; + value = JH8100_PADCFG_PU; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + return 0; + case PIN_CONFIG_INPUT_ENABLE: + mask = JH8100_PADCFG_IE; + value = arg ? JH8100_PADCFG_IE : 0; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask = JH8100_PADCFG_SMT; + value = arg ? JH8100_PADCFG_SMT : 0; + break; + default: + return -ENOTSUPP; + } + + jh8100_padcfg_rmw(sfp, gpio, mask, value); + } + + return 0; +} + +static int jh8100_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *config) +{ + const struct group_desc *group; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + return jh8100_pinconf_get(pctldev, group->grp.pins[0], config); +} + +static int jh8100_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *configs, + unsigned int num_configs) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *group; + u16 mask, value; + int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + mask = 0; + value = 0; + for (i = 0; i < num_configs; i++) { + int param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask |= JH8100_PADCFG_BIAS_MASK; + value &= ~JH8100_PADCFG_BIAS_MASK; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg == 0) + return -ENOTSUPP; + mask |= JH8100_PADCFG_BIAS_MASK; + value = (value & ~JH8100_PADCFG_BIAS_MASK) | JH8100_PADCFG_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg == 0) + return -ENOTSUPP; + mask |= JH8100_PADCFG_BIAS_MASK; + value = (value & ~JH8100_PADCFG_BIAS_MASK) | JH8100_PADCFG_PU; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + mask |= JH8100_PADCFG_DS_MASK; + value = (value & ~JH8100_PADCFG_DS_MASK) | + jh8100_padcfg_ds_from_mA(arg); + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + mask |= JH8100_PADCFG_DS_MASK; + value = (value & ~JH8100_PADCFG_DS_MASK) | + jh8100_padcfg_ds_from_uA(arg); + break; + case PIN_CONFIG_INPUT_ENABLE: + mask |= JH8100_PADCFG_IE; + if (arg) + value |= JH8100_PADCFG_IE; + else + value &= ~JH8100_PADCFG_IE; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask |= JH8100_PADCFG_SMT; + if (arg) + value |= JH8100_PADCFG_SMT; + else + value &= ~JH8100_PADCFG_SMT; + break; + case PIN_CONFIG_SLEW_RATE: + mask |= JH8100_PADCFG_SLEW; + if (arg) + value |= JH8100_PADCFG_SLEW; + else + value &= ~JH8100_PADCFG_SLEW; + break; + default: + return -ENOTSUPP; + } + } + + for (i = 0; i < group->grp.npins; i++) + jh8100_padcfg_rmw(sfp, group->grp.pins[i], mask, value); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void jh8100_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + u32 value; + int padcfg_base; + + padcfg_base = jh8100_get_padcfg_base(sfp, pin); + if (padcfg_base < 0) + return; + + value = readl_relaxed(sfp->base + padcfg_base + 4 * pin); + seq_printf(s, " (0x%02x)", value); +} +#else +#define jh8100_pinconf_dbg_show NULL +#endif + +static const struct pinconf_ops jh8100_pinconf_ops = { + .pin_config_get = jh8100_pinconf_get, + .pin_config_set = jh8100_pinconf_set, + .pin_config_group_get = jh8100_pinconf_group_get, + .pin_config_group_set = jh8100_pinconf_group_set, + .pin_config_dbg_show = jh8100_pinconf_dbg_show, + .is_generic = true, +}; + +static int jh8100_gpio_get_direction(struct gpio_chip *gc, + unsigned int gpio) +{ + struct jh8100_pinctrl *sfp = container_of(gc, + struct jh8100_pinctrl, gc); + const struct jh8100_pinctrl_domain_info *info = sfp->info; + unsigned int offset = 4 * (gpio / 4); + unsigned int shift = 8 * (gpio % 4); + u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); + + doen = (doen >> shift) & info->doen_mask; + + return doen == 0 ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + +static int jh8100_gpio_direction_input(struct gpio_chip *gc, + unsigned int gpio) +{ + struct jh8100_pinctrl *sfp = container_of(gc, + struct jh8100_pinctrl, gc); + + /* enable input and schmitt trigger */ + jh8100_padcfg_rmw(sfp, gpio, + JH8100_PADCFG_IE | JH8100_PADCFG_SMT, + JH8100_PADCFG_IE | JH8100_PADCFG_SMT); + + jh8100_set_one_pin_mux(sfp, gpio, 255, 0, 1, 0); + + return 0; +} + +static int jh8100_gpio_direction_output(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + struct jh8100_pinctrl *sfp = container_of(gc, + struct jh8100_pinctrl, gc); + + jh8100_set_one_pin_mux(sfp, gpio, + 255, value ? 1 : 0, + 0, 0); + + /* disable input, schmitt trigger and bias */ + jh8100_padcfg_rmw(sfp, gpio, + JH8100_PADCFG_IE | JH8100_PADCFG_SMT, + 0); + return 0; +} + +static int jh8100_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + struct jh8100_pinctrl *sfp = container_of(gc, + struct jh8100_pinctrl, gc); + const struct jh8100_pinctrl_domain_info *info = sfp->info; + void __iomem *reg = sfp->base + info->gpioin_reg_base + + 4 * (gpio / 32); + + return !!(readl_relaxed(reg) & BIT(gpio % 32)); +} + +static void jh8100_gpio_set(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + struct jh8100_pinctrl *sfp = container_of(gc, + struct jh8100_pinctrl, gc); + const struct jh8100_pinctrl_domain_info *info = sfp->info; + unsigned int offset = 4 * (gpio / 4); + unsigned int shift = 8 * (gpio % 4); + void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset; + u32 dout = (value ? 1 : 0) << shift; + u32 mask = info->dout_mask << shift; + unsigned long flags; + + raw_spin_lock_irqsave(&sfp->lock, flags); + dout |= readl_relaxed(reg_dout) & ~mask; + writel_relaxed(dout, reg_dout); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void jh8100_irq_ack(struct irq_data *d) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + const struct jh8100_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ic = sfp->base + irq_reg->ic_reg_base + + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ic) & ~mask; + writel_relaxed(value, ic); + writel_relaxed(value | mask, ic); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void jh8100_irq_mask(struct irq_data *d) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + const struct jh8100_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ie = sfp->base + irq_reg->ie_reg_base + + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ie) & ~mask; + writel_relaxed(value, ie); + raw_spin_unlock_irqrestore(&sfp->lock, flags); + + gpiochip_disable_irq(&sfp->gc, d->hwirq); +} + +static void jh8100_irq_mask_ack(struct irq_data *d) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + const struct jh8100_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ie = sfp->base + irq_reg->ie_reg_base + + 4 * (gpio / 32); + void __iomem *ic = sfp->base + irq_reg->ic_reg_base + + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ie) & ~mask; + writel_relaxed(value, ie); + + value = readl_relaxed(ic) & ~mask; + writel_relaxed(value, ic); + writel_relaxed(value | mask, ic); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void jh8100_irq_unmask(struct irq_data *d) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + const struct jh8100_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ie = sfp->base + irq_reg->ie_reg_base + + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + gpiochip_enable_irq(&sfp->gc, d->hwirq); + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ie) | mask; + writel_relaxed(value, ie); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static int jh8100_irq_set_type(struct irq_data *d, unsigned int trigger) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + const struct jh8100_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *base = sfp->base + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + u32 irq_type, edge_both, polarity; + unsigned long flags; + + switch (trigger) { + case IRQ_TYPE_EDGE_RISING: + irq_type = mask; /* 1: edge triggered */ + edge_both = 0; /* 0: single edge */ + polarity = mask; /* 1: rising edge */ + break; + case IRQ_TYPE_EDGE_FALLING: + irq_type = mask; /* 1: edge triggered */ + edge_both = 0; /* 0: single edge */ + polarity = 0; /* 0: falling edge */ + break; + case IRQ_TYPE_EDGE_BOTH: + irq_type = mask; /* 1: edge triggered */ + edge_both = mask; /* 1: both edges */ + polarity = 0; /* 0: ignored */ + break; + case IRQ_TYPE_LEVEL_HIGH: + irq_type = 0; /* 0: level triggered */ + edge_both = 0; /* 0: ignored */ + polarity = mask; /* 1: high level */ + break; + case IRQ_TYPE_LEVEL_LOW: + irq_type = 0; /* 0: level triggered */ + edge_both = 0; /* 0: ignored */ + polarity = 0; /* 0: low level */ + break; + default: + return -EINVAL; + } + + if (trigger & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(d, handle_edge_irq); + else + irq_set_handler_locked(d, handle_level_irq); + + raw_spin_lock_irqsave(&sfp->lock, flags); + irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask; + writel_relaxed(irq_type, base + irq_reg->is_reg_base); + + edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask; + writel_relaxed(edge_both, base + irq_reg->ibe_reg_base); + + polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask; + writel_relaxed(polarity, base + irq_reg->iev_reg_base); + raw_spin_unlock_irqrestore(&sfp->lock, flags); + return 0; +} + +static int jh8100_irq_set_wake(struct irq_data *d, unsigned int enable) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + int ret = 0; + + if (enable) + ret = enable_irq_wake(sfp->wakeup_irq); + else + ret = disable_irq_wake(sfp->wakeup_irq); + if (ret) + dev_err(sfp->dev, "failed to %s wake-up interrupt\n", + enable ? "enable" : "disable"); + + return ret; +} + +static void jh8100_irq_print_chip(struct irq_data *d, struct seq_file *p) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + + seq_printf(p, sfp->gc.label); +} + +static const struct irq_chip jh8100_irq_chip = { + .irq_ack = jh8100_irq_ack, + .irq_mask = jh8100_irq_mask, + .irq_mask_ack = jh8100_irq_mask_ack, + .irq_unmask = jh8100_irq_unmask, + .irq_set_type = jh8100_irq_set_type, + .irq_set_wake = jh8100_irq_set_wake, + .irq_print_chip = jh8100_irq_print_chip, + .flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_IMMUTABLE | + IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | + IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SKIP_SET_WAKE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static void jh8100_gpio_irq_handler(struct irq_desc *desc) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_desc(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct gpio_irq_chip *girq = &sfp->gc.irq; + unsigned long mis; + unsigned int pin; + + chained_irq_enter(chip, desc); + + mis = readl_relaxed(sfp->base + sfp->info->irq_reg->mis_reg_base); + for_each_set_bit(pin, &mis, sfp->info->mis_pin_num) + generic_handle_domain_irq(girq->domain, pin); + + if (sfp->info->irq_reg->mis1_reg_base) { + mis = readl_relaxed(sfp->base + sfp->info->irq_reg->mis1_reg_base); + for_each_set_bit(pin, &mis, sfp->info->mis1_pin_num) + generic_handle_domain_irq(girq->domain, pin + 32); + } + + chained_irq_exit(chip, desc); +} + +static int jh8100_gpio_init_hw(struct gpio_chip *gc) +{ + struct jh8100_pinctrl *sfp = container_of(gc, + struct jh8100_pinctrl, gc); + + /* mask all GPIO interrupts */ + writel_relaxed(0U, sfp->base + sfp->info->irq_reg->ie_reg_base); + /* clear edge interrupt flags */ + writel_relaxed(0U, sfp->base + sfp->info->irq_reg->ic_reg_base); + writel_relaxed(~0U, sfp->base + sfp->info->irq_reg->ic_reg_base); + if (sfp->info->irq_reg->ic1_reg_base) { + writel_relaxed(0U, sfp->base + sfp->info->irq_reg->ic1_reg_base); + writel_relaxed(~0U, sfp->base + sfp->info->irq_reg->ic1_reg_base); + } + /* enable GPIO interrupts */ + writel_relaxed(1, sfp->base + sfp->info->irq_reg->ien_reg_base); + + return 0; +} + +static void jh8100_disable_clock(void *data) +{ + clk_disable_unprepare(data); +} + +int jh8100_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct gpio_irq_chip *girq; + const struct jh8100_pinctrl_domain_info *info; + struct jh8100_pinctrl *sfp; + struct pinctrl_desc *jh8100_pinctrl_desc; + struct reset_control *rst; + struct clk *clk; + int ret; + + info = of_device_get_match_data(&pdev->dev); + if (!info) + return -ENODEV; + + sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL); + if (!sfp) + return -ENOMEM; + + sfp->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sfp->base)) + return PTR_ERR(sfp->base); + + clk = devm_clk_get_optional(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n"); + + rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), "could not get reset control\n"); + + ret = clk_prepare_enable(clk); + if (ret) + return dev_err_probe(dev, ret, "could not enable clock\n"); + + ret = devm_add_action_or_reset(dev, jh8100_disable_clock, clk); + if (ret) + return ret; + + /* + * we don't want to assert reset and risk undoing pin muxing for the + * early boot serial console, but let's make sure the reset line is + * deasserted in case someone runs a really minimal bootloader. + */ + ret = reset_control_deassert(rst); + if (ret) + return dev_err_probe(dev, ret, "could not deassert reset\n"); + + jh8100_pinctrl_desc = devm_kzalloc(&pdev->dev, + sizeof(*jh8100_pinctrl_desc), + GFP_KERNEL); + if (!jh8100_pinctrl_desc) + return -ENOMEM; + + jh8100_pinctrl_desc->name = dev_name(dev); + jh8100_pinctrl_desc->pins = info->pins; + jh8100_pinctrl_desc->npins = info->npins; + jh8100_pinctrl_desc->pctlops = &jh8100_pinctrl_ops; + jh8100_pinctrl_desc->pmxops = &jh8100_pinmux_ops; + jh8100_pinctrl_desc->confops = &jh8100_pinconf_ops; + jh8100_pinctrl_desc->owner = THIS_MODULE; + + sfp->info = info; + sfp->dev = dev; + platform_set_drvdata(pdev, sfp); + sfp->gc.parent = dev; + raw_spin_lock_init(&sfp->lock); + mutex_init(&sfp->mutex); + + ret = devm_pinctrl_register_and_init(dev, + jh8100_pinctrl_desc, + sfp, &sfp->pctl); + if (ret) + return dev_err_probe(dev, ret, + "could not register pinctrl driver\n"); + + sfp->gc.label = dev_name(dev); + sfp->gc.owner = THIS_MODULE; + sfp->gc.request = pinctrl_gpio_request; + sfp->gc.free = pinctrl_gpio_free; + sfp->gc.get_direction = jh8100_gpio_get_direction; + sfp->gc.direction_input = jh8100_gpio_direction_input; + sfp->gc.direction_output = jh8100_gpio_direction_output; + sfp->gc.get = jh8100_gpio_get; + sfp->gc.set = jh8100_gpio_set; + sfp->gc.set_config = gpiochip_generic_config; + sfp->gc.base = info->gc_base; + sfp->gc.ngpio = info->ngpios; + + girq = &sfp->gc.irq; + + if (info->irq_reg) { + gpio_irq_chip_set_chip(girq, &jh8100_irq_chip); + girq->parent_handler = jh8100_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, girq->num_parents, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + girq->init_hw = jh8100_gpio_init_hw; + + ret = platform_get_irq(pdev, 0); + if (ret < 0) + return ret; + girq->parents[0] = ret; + } + + ret = pinctrl_enable(sfp->pctl); + if (ret) + return ret; + + if (sfp->gc.ngpio > 0) { + ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp); + if (ret) + return dev_err_probe(dev, ret, "could not register gpiochip\n"); + + dev_info(dev, "StarFive JH8100 GPIO chip registered %d GPIOs\n", sfp->gc.ngpio); + } + + return 0; +} +EXPORT_SYMBOL_GPL(jh8100_pinctrl_probe); + +MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH8100 SoC"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h new file mode 100644 index 000000000000..6eb4f1896a90 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#ifndef __PINCTRL_STARFIVE_JH8100_H__ +#define __PINCTRL_STARFIVE_JH8100_H__ + +#include "../core.h" + +#define JH8100_SYS_E_DOMAIN_NAME "jh8100-sys-east" + +#define JH8100_SYS_E_NGPIO 48 + +#define JH8100_SYS_E_REG_NUM 116 + +#define JH8100_SYS_E_GPO_PDA_00_47_CFG 0x114 + +struct jh8100_pinctrl { + struct device *dev; + struct gpio_chip gc; + struct pinctrl_gpio_range gpios; + raw_spinlock_t lock; + void __iomem *base; + struct pinctrl_dev *pctl; + /* register read/write mutex */ + struct mutex mutex; + const struct jh8100_pinctrl_domain_info *info; + unsigned int jh8100_sys_east_regs[JH8100_SYS_E_REG_NUM]; + /* wakeup */ + struct irq_domain *irq_domain; + struct gpio_desc *wakeup_gpio; + int wakeup_irq; +}; + +struct jh8100_gpio_func_sel { + unsigned short offset; + unsigned char shift; + unsigned char max; +}; + +struct jh8100_gpio_irq_reg { + unsigned int is_reg_base; + unsigned int ic_reg_base; + unsigned int ic1_reg_base; + unsigned int ibe_reg_base; + unsigned int iev_reg_base; + unsigned int ie_reg_base; + unsigned int ris_reg_base; + unsigned int mis_reg_base; + unsigned int mis1_reg_base; + unsigned int ien_reg_base; +}; + +struct jh8100_pinctrl_domain_info { + const struct pinctrl_pin_desc *pins; + unsigned int npins; + unsigned int ngpios; + unsigned int gc_base; + + const char *name; + unsigned int nregs; + + /* gpio dout/doen/din/gpioinput register */ + unsigned int dout_reg_base; + unsigned int dout_mask; + unsigned int doen_reg_base; + unsigned int doen_mask; + unsigned int gpi_reg_base; + unsigned int gpi_mask; + unsigned int gpioin_reg_base; + + const struct jh8100_gpio_func_sel *func_sel; + const struct jh8100_gpio_irq_reg *irq_reg; + + /* gpio chip */ + unsigned int mis_pin_num; + unsigned int mis1_pin_num; +}; + +int jh8100_pinctrl_probe(struct platform_device *pdev); +void jh8100_set_gpiomux(struct jh8100_pinctrl *sfp, unsigned int pin, + unsigned int din, u32 dout, u32 doen); +struct jh8100_pinctrl *jh8100_from_irq_desc(struct irq_desc *desc); +void pinctrl_utils_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned int num_maps); +int pinmux_generic_get_function_count(struct pinctrl_dev *pctldev); +const char *pinmux_generic_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector); +int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups); +int pinmux_generic_add_function(struct pinctrl_dev *pctldev, + const char *name, + const char * const *groups, + unsigned int const num_groups, + void *data); + +#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_OF) +int pinconf_generic_parse_dt_config(struct device_node *np, + struct pinctrl_dev *pctldev, + unsigned long **configs, + unsigned int *nconfigs); +#endif + +#endif /* __PINCTRL_STARFIVE_JH8100_H__ */ From patchwork Fri May 3 11:14:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuklin Soo X-Patchwork-Id: 13652672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BFCDC10F16 for ; Fri, 3 May 2024 11:15:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xx0nZFTTXiANPIrN8BfJ9k/L1DLk1k4udba8eXCBw94=; b=S13PSHUMkPCQML fNuR17aV0cl7zKugATXIFgUM0nOfz50MSr2wn0QZen9P0I6IJTYJNk9hrFUl4OzcG5UoaIpNwuKiR 87qRndWnXo+KiNuTMh0gbW/qRxP0TMQXCK3U+UtDLq8SSahkSeu4gtpQ5MMzIElYpm/7kAfoaEUMO 3TwmGvdc5GtURkfbO0m0dzHRXRYj1EV3DZ+/Itj1ZdLZ/HkcV/nGqVYxeXzElZtHLJ+CTf0s4UqMi rgK7H/X1aSakFE0WkoJN0THuSdr8pQ7gqBmy2ajjNj7A3jNG3uLA2jU/+BOohBLl9T4pAXY3BBuZu KoRGftR62P+vLVfGYq+w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qse-0000000GD2d-0NuS; Fri, 03 May 2024 11:15:08 +0000 Received: from mail-sh0chn02on20708.outbound.protection.partner.outlook.cn ([2406:e500:4420:2::708] helo=CHN02-SH0-obe.outbound.protection.partner.outlook.cn) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qsa-0000000GCxl-1DkI for linux-riscv@lists.infradead.org; Fri, 03 May 2024 11:15:06 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Yc6emfCmmDOaSNi28/XZ36qJiEN5xlMtx7/4sBurXVbKkGtA3bFXuU9lzuLB056zPlcEtIodUikXz+S3XcJk3tWN1capU0umaZQRMt3V5Z6jTRj5S57zS3lRw4rQIrc1dY82q9JxUp56tSr/uAxayB3HAuMCYjzhzZHpYfKZpt1Hcya7Pe2mLCLWgptMpmh7/7tQZNJ0vzO2AZI4XacuZeVkHgAtkNYd4uSrk+fJUIGaHjq7x9sX0ciWytYPMPlUtrT6cUZ+4T7GiK4tjtR+oVKpxtRRRuAs3RxX4bvU6LVGI61LVQ5XhhW/pTUQ9P9CGfORjfE85zzDoVtpBEot7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=A4jb7iFCnA3QDskpBV8VGbbtzV1NunIi753ciHo9LA8=; b=PBpisGU65Dt0urmk38HKq1cOhgFwgIAjGhsPAhQWQ17Dc/ApwHlXSuSeK7jPPOWkEq30ipyUR979Ib7pBfewcme1UxrjG8SLBwR42sZSNRQaWcHjQH5eiE6lv2cYXdpRzc9ThnoNNnW/mtt+qCNtp1ugHxt+A54ydfmKf4psqx9OyzTPi9dcf5G3X/7rDWYIqqqunZh30aq+g/So79OPejhWnVpdtWr8CeezvUftkq0oNn1naGqwfRRCF8CxHTCAe86e/gss9of1nxj0ngvIvu/sZbbiFo6FVPe3WIDyoRwwBZmsbneWgUalfguRYEwLf3A155k6CB+MfrnkOAJGfQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) by ZQ0PR01MB1238.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:1b::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Fri, 3 May 2024 11:14:56 +0000 Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4]) by ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4%5]) with mapi id 15.20.7472.044; Fri, 3 May 2024 11:14:56 +0000 From: Alex Soo To: Linus Walleij , Bartosz Golaszewski , Hal Feng , Ley Foon Tan , Jianlong Huang , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alex Soo Subject: [RFC PATCH v3 3/7] pinctrl: starfive: jh8100: add sys_west domain sub-driver Date: Fri, 3 May 2024 19:14:32 +0800 Message-Id: <20240503111436.113089-4-yuklin.soo@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240503111436.113089-1-yuklin.soo@starfivetech.com> References: <20240503111436.113089-1-yuklin.soo@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0011.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::20) To ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1176:EE_|ZQ0PR01MB1238:EE_ X-MS-Office365-Filtering-Correlation-Id: d12fe879-e9cc-4afe-dda7-08dc6b62434b X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: U51KBppsyaMNg4IC/g5pQ90fRSAsK09+VMlb7wgqPrUbA0we6UjC66YazeXvxFGDHq3CZ2hTIWz7Jr3xG7qouQ1tcNdJhgTPuWberl5PiTdeKajc0yfWzJc55DdfIynBOql/Wi68Rq4iCjXgR1MCoK5Beu8U2ryb7X+lhIvNgbtnpbnjlNexC0oEFZMandGll61BAn/84D2z+gOTRz5a1KqkaV2YqiFiKwwo+d8lay39tzssnyHjnozz/qnT0HxugIuu4VhjYt/F9903X2GjKMYHloFlu5kh8GDljSpyFU/dqtnk9AxpWlUqVMS7fR5aSkYVsyfEdwzttFm//DzfKtDBVzhos8m3SZB0iFgLXGAD2PDq2rnX68w9pQsKcPB6461ET44Lh5h+p9hlTDEylvx91L2a4ush5brBsyGUxawdNmqgCmSy2v+adwjk+gOXEzeOfpPj6J+FSL7utUIJ8wohyXWANENC4z+myq4A/b//fyGNup9iq/KJt1BEcg1rPHSDgKGvZLH6wnwUDUHShaMyEqM7Qh42Eeu5gQn/GOVh39E231BYCPidBYcgj+n2nGjSPZaIx4CxPWDqlFOfZwhsd0aZ2DLx06RvSskkHz+4Z8lkNeJuoHRmGVF2bexw4b+5myLW4u+9tXvJPMiZ7g== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230031)(52116005)(41320700004)(7416005)(366007)(1800799015)(38350700005)(921011);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xw0xFhWEZzb3s9qqQ9Qj8DWMV/5Nev6px5oGNZTna1FQcp3sGVNG8VQ0TgnYx0+yKyi8/COoKKNMKJoXgmKq331eUpEBqXqCYToCFT0aWvvkj2hjxb37linxfMjKZ0xGnIMDDP9MV7x4Sfu5Lq25s/GREACNucEg9DxulkW7haSrypkdAu8c3omiXBVUPMRFKcMwiMtKxMZ2j7KytfkVsBvvEg/bNbllVY/v7pN2tnqMy/yLo3Qi9xGbBQorOflXPSAg5s2DripEyOGl9pEU+MZMKU3CrIJq94BmnDQlP3IsYpZEGQL0BfJjGjdJBTzXYQbwP83dsz+brI30ibI5qke8VdmYgVJ7AjOizM55KY/zOFxfKaFznsJauK2PjvA00699CIMJf1HTy47BY0lTFnEnXQGvdCo5lYKJiK3bAiGuuQq/1R6dCfh0dPj5EltL+lMSTB0VyiJg5BhZI/ndRE2n5NZrMHvEXKNlFJUU7riMTvU07GZzO73rgUm7UL/mx5pECBRabU88jZkcDolRuxm8RlKfm1a8yV5X+hHWPjR1ezQev1e6cZeFfBNWZwAwgizAKuruwPkRl0INeH80FbGtjOzUyfvxpm0B25VPzIcR1WIgPe1pFHzIuwxF1/4r2Ik+icWAX1vmkMM6Ycia2Yv59evcqt+KixIASWpVZmVs/EiNxKIP5+Yea4PXr10ayt7feRuRkeUt5OWqZyt+mfw89NxsdqR7xbRzWcAvivr/nPKGRBEdKoPo9ifEMcYjWJOEw7Rx3k6SiXj1kOOqTwNCXELxvW9m+rfZPecOydFlbgyHuz5WJ9dc89mgFQducMGDrT7/2o3jjpEdSspuzFAl9vQpLPjU6JB302GRoJbQectorBvNcHNIkSljV7kVRblvZ5BsFZ67q9yNmbJ8L4EIQhyUfzncZN70DZRjb3Q3PFMymf7218PBFQVD/recdka4M/HJRURXj1rO/rFRSB365J/ytJipaRNwWuDbCDrgymymYKYLTTufzKlA6PJSRbu2apwR9e2VLMqGqFOOvs0a0jtSfcyn+XnRX0+DU1mqsBK9FbUQKUjvsVu8xOA8HinFGxOjbDowEbb4Xm4CC53e3f2eI/vAcxqC8cGKMMQxx5p3VNPK+TOHST97yLPHdx9V9BeagiX4QdfP5+Caf/66jFowOzb6qHkF2/p16osgftQ3CzFXr5LsGUqAz817X2q4SdN+427m9tr91IjxDp+0a/1uCPMs1w6iSVfQS6VA60wCLv5walnPpmxCkmNfuGQgQAJJV885fzUTA57fQRPJjB8deRVB6OapQM7jBMkpDPv+QmIdXWRnnnaZpK9xuXRaUMDdIRowAssFcjxORmA4YuRTuT2YtwwZMnQ3obYEg6b1XTuFTxVsnYGeGPliDzF4y0J+IsgxbOjZowhv66XsWZg+6SZLgypLNcDVW2yxpKAx4BsPqemDDlpAx0IBsMqsynwvlexspGGmIA6VSqs9CNLZV84/h8GATz9dfWtg8FDPGKlShgVYOeZvdaWuPwAqQOd15cgVOpmgFzrb/lWdNnc5/yK6OnvqQs/8HFH/McaJfrqjTgNauTcqOI6N3icCbD9ATb1bkcjsLNMVGw== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: d12fe879-e9cc-4afe-dda7-08dc6b62434b X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 11:14:56.0756 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: uXFjiYlC6YSZd5Xk7hS+bK4jGc6fY/Zpdc27ERRDV9PKQxWEk4Js4js+IfaaoiVk6QjRZGhFd0anXwImHASt0vjOFkwOMo76teJMdxseruY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1238 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240503_041504_653808_D1344C49 X-CRM114-Status: GOOD ( 22.26 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add sys_west domain sub-driver. Signed-off-by: Alex Soo --- drivers/pinctrl/starfive/Kconfig | 12 ++ drivers/pinctrl/starfive/Makefile | 1 + .../pinctrl-starfive-jh8100-sys-west.c | 164 ++++++++++++++++++ .../starfive/pinctrl-starfive-jh8100.c | 6 + .../starfive/pinctrl-starfive-jh8100.h | 5 + 5 files changed, 188 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-west.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index afcbf9d4dc8d..d78f161a636c 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -70,3 +70,15 @@ config PINCTRL_STARFIVE_JH8100_SYS_EAST This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JH8100_SYS_WEST + tristate "StarFive JH8100 SoC System IOMUX-West pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + depends on OF + select PINCTRL_STARFIVE_JH8100 + default ARCH_STARFIVE + help + Say yes here to support system iomux-west pin control on the StarFive JH8100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index 45698c502b48..784465157ae2 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100) += pinctrl-starfive-jh8100.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_EAST) += pinctrl-starfive-jh8100-sys-east.o +obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_WEST) += pinctrl-starfive-jh8100-sys-west.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-west.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-west.c new file mode 100644 index 000000000000..b97d89777aa3 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-west.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC sys west controller + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include +#include +#include +#include + +#include + +#include "pinctrl-starfive-jh8100.h" + +#define JH8100_SYS_W_GC_BASE 0 + +/* registers */ +#define JH8100_SYS_W_DOEN 0x000 +#define JH8100_SYS_W_DOUT 0x010 +#define JH8100_SYS_W_GPI 0x020 +#define JH8100_SYS_W_GPIOIN 0x068 + +#define JH8100_SYS_W_GPIOEN 0x048 +#define JH8100_SYS_W_GPIOIS0 0x04c +#define JH8100_SYS_W_GPIOIC0 0x050 +#define JH8100_SYS_W_GPIOIBE0 0x054 +#define JH8100_SYS_W_GPIOIEV0 0x058 +#define JH8100_SYS_W_GPIOIE0 0x05c +#define JH8100_SYS_W_GPIORIS0 0x060 +#define JH8100_SYS_W_GPIOMIS0 0x064 + +static const struct pinctrl_pin_desc jh8100_sys_w_pins[] = { + PINCTRL_PIN(0, "SYS_W_GPIO0"), + PINCTRL_PIN(1, "SYS_W_GPIO1"), + PINCTRL_PIN(2, "SYS_W_GPIO2"), + PINCTRL_PIN(3, "SYS_W_GPIO3"), + PINCTRL_PIN(4, "SYS_W_GPIO4"), + PINCTRL_PIN(5, "SYS_W_GPIO5"), + PINCTRL_PIN(6, "SYS_W_GPIO6"), + PINCTRL_PIN(7, "SYS_W_GPIO7"), + PINCTRL_PIN(8, "SYS_W_GPIO8"), + PINCTRL_PIN(9, "SYS_W_GPIO9"), + PINCTRL_PIN(10, "SYS_W_GPIO10"), + PINCTRL_PIN(11, "SYS_W_GPIO11"), + PINCTRL_PIN(12, "SYS_W_GPIO12"), + PINCTRL_PIN(13, "SYS_W_GPIO13"), + PINCTRL_PIN(14, "SYS_W_GPIO14"), + PINCTRL_PIN(15, "SYS_W_GPIO15"), +}; + +static const struct jh8100_gpio_func_sel + jh8100_sys_w_func_sel[ARRAY_SIZE(jh8100_sys_w_pins)] = { + [0] = { 0xb4, 0, 2 }, + [1] = { 0xb4, 12, 2 }, + [2] = { 0xb4, 14, 2 }, + [3] = { 0xb4, 16, 2 }, + [4] = { 0xb4, 18, 2 }, + [5] = { 0xb4, 20, 2 }, + [6] = { 0xb4, 22, 2 }, + [7] = { 0xb4, 24, 2 }, + [8] = { 0xb4, 26, 2 }, + [9] = { 0xb4, 28, 2 }, + [10] = { 0xb4, 2, 2 }, + [11] = { 0xb4, 4, 2 }, + [12] = { 0xb4, 6, 2 }, + [13] = { 0xb4, 8, 2 }, + [14] = { 0xb4, 10, 2 }, +}; + +#ifdef CONFIG_PM_SLEEP +static int jh8100_sys_w_pinctrl_suspend(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + sfp->jh8100_sys_west_regs[i] = readl_relaxed(sfp->base + (i * 4)); + + return pinctrl_force_sleep(sfp->pctl); +} + +static int jh8100_sys_w_pinctrl_resume(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + writel_relaxed(sfp->jh8100_sys_west_regs[i], sfp->base + (i * 4)); + + return pinctrl_force_default(sfp->pctl); +} +#endif + +static SIMPLE_DEV_PM_OPS(jh8100_sys_w_pinctrl_dev_pm_ops, + jh8100_sys_w_pinctrl_suspend, + jh8100_sys_w_pinctrl_resume); + +static const struct jh8100_gpio_irq_reg jh8100_sys_w_irq_reg = { + .is_reg_base = JH8100_SYS_W_GPIOIS0, + .ic_reg_base = JH8100_SYS_W_GPIOIC0, + .ibe_reg_base = JH8100_SYS_W_GPIOIBE0, + .iev_reg_base = JH8100_SYS_W_GPIOIEV0, + .ie_reg_base = JH8100_SYS_W_GPIOIE0, + .ris_reg_base = JH8100_SYS_W_GPIORIS0, + .mis_reg_base = JH8100_SYS_W_GPIOMIS0, + .ien_reg_base = JH8100_SYS_W_GPIOEN, +}; + +static const struct jh8100_pinctrl_domain_info jh8100_sys_w_pinctrl_info = { + .pins = jh8100_sys_w_pins, + .npins = ARRAY_SIZE(jh8100_sys_w_pins), + .ngpios = JH8100_SYS_W_NGPIO, + .gc_base = JH8100_SYS_W_GC_BASE, + .name = JH8100_SYS_W_DOMAIN_NAME, + .nregs = JH8100_SYS_W_REG_NUM, + .dout_reg_base = JH8100_SYS_W_DOUT, + .dout_mask = GENMASK(5, 0), + .doen_reg_base = JH8100_SYS_W_DOEN, + .doen_mask = GENMASK(4, 0), + .gpi_reg_base = JH8100_SYS_W_GPI, + .gpi_mask = GENMASK(4, 0), + .gpioin_reg_base = JH8100_SYS_W_GPIOIN, + .func_sel = jh8100_sys_w_func_sel, + .irq_reg = &jh8100_sys_w_irq_reg, + .mis_pin_num = JH8100_SYS_W_NGPIO, +}; + +static const struct of_device_id jh8100_sys_w_pinctrl_of_match[] = { + { + .compatible = "starfive,jh8100-sys-pinctrl-west", + .data = &jh8100_sys_w_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh8100_sys_w_pinctrl_of_match); + +static struct platform_driver jh8100_sys_w_pinctrl_driver = { + .probe = jh8100_pinctrl_probe, + .driver = { + .name = "starfive-jh8100-sys-pinctrl-west", +#ifdef CONFIG_PM_SLEEP + .pm = &jh8100_sys_w_pinctrl_dev_pm_ops, +#endif + .of_match_table = jh8100_sys_w_pinctrl_of_match, + }, +}; +module_platform_driver(jh8100_sys_w_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JH8100 SoC sys west controller"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c index 4b68463ff5a5..8c3e4a90d68d 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c @@ -333,6 +333,9 @@ static int jh8100_set_one_pin_mux(struct jh8100_pinctrl *sfp, if (!strcmp(sfp->info->name, JH8100_SYS_E_DOMAIN_NAME) && pin < sfp->gc.ngpio && func == 1) jh8100_set_function(sfp, pin, func); + else if (!strcmp(sfp->info->name, JH8100_SYS_W_DOMAIN_NAME) && + pin < sfp->gc.ngpio - 1 && func == 2) + jh8100_set_function(sfp, pin, func); return 0; } @@ -410,6 +413,9 @@ static int jh8100_get_padcfg_base(struct jh8100_pinctrl *sfp, if (!strcmp(sfp->info->name, JH8100_SYS_E_DOMAIN_NAME)) { if (pin < JH8100_SYS_E_NGPIO) return JH8100_SYS_E_GPO_PDA_00_47_CFG; + } else if (!strcmp(sfp->info->name, JH8100_SYS_W_DOMAIN_NAME)) { + if (pin < JH8100_SYS_W_NGPIO) + return JH8100_SYS_W_GPO_PDA_00_15_CFG; } return -ENXIO; diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h index 6eb4f1896a90..7c7a05c1c828 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h @@ -12,12 +12,16 @@ #include "../core.h" +#define JH8100_SYS_W_DOMAIN_NAME "jh8100-sys-west" #define JH8100_SYS_E_DOMAIN_NAME "jh8100-sys-east" +#define JH8100_SYS_W_NGPIO 16 #define JH8100_SYS_E_NGPIO 48 +#define JH8100_SYS_W_REG_NUM 44 #define JH8100_SYS_E_REG_NUM 116 +#define JH8100_SYS_W_GPO_PDA_00_15_CFG 0x074 #define JH8100_SYS_E_GPO_PDA_00_47_CFG 0x114 struct jh8100_pinctrl { @@ -30,6 +34,7 @@ struct jh8100_pinctrl { /* register read/write mutex */ struct mutex mutex; const struct jh8100_pinctrl_domain_info *info; + unsigned int jh8100_sys_west_regs[JH8100_SYS_W_REG_NUM]; unsigned int jh8100_sys_east_regs[JH8100_SYS_E_REG_NUM]; /* wakeup */ struct irq_domain *irq_domain; From patchwork Fri May 3 11:14:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuklin Soo X-Patchwork-Id: 13652670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8C5EC25B5C for ; Fri, 3 May 2024 11:15:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5tRpWOtwcfyA/8ganeJL65K5Z13lQ5ZhLaW7CqG4ymA=; b=GBaoANJVWe+y+M QQy3Ee68a1djDWKWeNPscLCcKbwPeyQvTdK5R4Z2GCMHasDzqUgRWEjxhDjLeWYck+7Bz7JZDPW/x G3qRHaW/X5+eFmAw5q7OjLiqCdEQxLu5EdJMAy8i3Z4OS0r4lx7IwEKXnp6LAzStBXN15A7oE1lA6 ZFHEC+QXjUZ0sUcZt5R5T8S71Z2rl4X70XLEPKCPPFCZqGy3fR3faKS+dNG8Lyjr7h/osyGkVlcLw M1nM39+Urxmy+BM225QGe7XXTCKvqPhZrEuiHubBAltO/S8hbhCDXaDXPSrM3/6kF6kdLdVQXR10l Q1DZ+WbGV0en48mQnv2w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qse-0000000GD2w-3UOt; Fri, 03 May 2024 11:15:08 +0000 Received: from mail-sh0chn02on20708.outbound.protection.partner.outlook.cn ([2406:e500:4420:2::708] helo=CHN02-SH0-obe.outbound.protection.partner.outlook.cn) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qsc-0000000GCxl-2VHB for linux-riscv@lists.infradead.org; Fri, 03 May 2024 11:15:07 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Bq6pobkJ+VnTrnfwfi0GzZXMl4YH5b+tdGSe5vqIwhQSn4OUiLd9slAhmdYn9pWEiYisPww+NX1E02zkDqxu1LlCPP3rpCdQbi8MzBgBXMzi4JUELbD+/SQV76SkjzvridqDSGwkkfDmtDYIhpnQy4aMGodX3zSN+dTjS961LW1/6EghCq8TnNFzaq6cTQjFj7U619e9cHIV869RQfNsDFOfWiyp5f14qQmeSZaciRqUdx7bdHhb8vfDxWdCugNSVYntDCPjfA9VJN7vlb2U3V09rvGadEVOU3pmISvloGtkiB2u9JHixPRo5V1uXxrD/7wzvUXlIyM7e8VbcM/elA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=g+kPXEwFOk6Vk6fj8TZBhGJ/JG1x9D8pU73iMkL4xfE=; b=lhsdWqIodwjDnN1Q+onQwgd16Ty4n2OGOE11kTafBFo4Bgd45YR92OnfByao2nHBl0W/ZdpCWIOH0Cxb4/xsr3FNfIhbTj63Sb1x0ZdpeGNS4DfgQVtXvUBK/ral5PGGyLERMPgWc8Rh6TAKGHMPHz2z9e3GQMMrPCG9xGvh0QwbfhzDZMY4vwf9d/sog5zuqUiqCWWlvUo8q02EiK/sxTAzId9ZEjQ0wGEHzQ68cxDtImXEVPEXI3a1SBf9FBbtk/SE6NRmqtsBwYh6lce910uuRzUy9gjaecos0KbAOCmZJOrVTDt6BQkUE7PNKiOywnJDTuCVM0lMs0mcGvCmwg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) by ZQ0PR01MB1238.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:1b::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Fri, 3 May 2024 11:14:59 +0000 Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4]) by ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4%5]) with mapi id 15.20.7472.044; Fri, 3 May 2024 11:14:59 +0000 From: Alex Soo To: Linus Walleij , Bartosz Golaszewski , Hal Feng , Ley Foon Tan , Jianlong Huang , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alex Soo Subject: [RFC PATCH v3 4/7] pinctrl: starfive: jh8100: add sys_gmac domain sub-driver Date: Fri, 3 May 2024 19:14:33 +0800 Message-Id: <20240503111436.113089-5-yuklin.soo@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240503111436.113089-1-yuklin.soo@starfivetech.com> References: <20240503111436.113089-1-yuklin.soo@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0011.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::20) To ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1176:EE_|ZQ0PR01MB1238:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d7faab7-cbef-46ae-ceca-08dc6b624517 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LZxcT0xyLFmYe0ZJJTvXCd09ilen3M5IsP1qhP6c0ayaEhycrIoO/7YnSI0kfUq5j1iwCEsaB1nJvD5B7lRZfA/0rWGeKedsEQhMaG5MNldKCR00R2R4JwvwuJ62VdvXFeElNvsCl6sxeqNcCmWcoQpW8K2xqbDSb0Hjs8TIjGGWe6fgteeIg1WXaz9ZgEA01df/YoPsmpNQ6IpddSHizn4eHn+7nTk0mU4LFZ0ZX3+J3loB+R5qaHPJ8XQAC3Zlh6j0Xmrx1yveKyzH5n4YLhAWz+RknB6FAW2tqr+LMzf3gfS6aE2c6uz2P7hMqsLx9YL7OJGvmaJxJXJA7ujfqY5OnxCOP3VhIXdYk4RhqxJqc5ismJPtkZQAAA+KYvUtXCd0Ql742YP3Ia7+mSlg9K9ZXm+mOZZErMKcJv7ceOo538GV4YV3d9ONs3mezgcun5V2UMpOyvIjmFgcxwDbZTXiKdKkRvnaQvHGud/IjfmzPLn6meTFie3jKahiKjzkIX48zKGfAf011unlKAaJ2uu0vtQZm1xvOdaQVDRDu+zDIDbJdeQ3GthNumMiotv48BZTLoKGk+D7K73IW4nTgbLnvLGmxHBDaIgJxkekl6BxoSCKJiulAAG+qoq1W3ADF6FRmikDy0yJOoXzZdEDfw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230031)(52116005)(41320700004)(7416005)(366007)(1800799015)(38350700005)(921011);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tnQ7ZEx9FEyHPY+iw38HlOwBhTmLy0IhnlzhEyAy0yETKuljK/HLtMC5TLzz+7SwSwkhRc9bBrNAjkClsbsVODm4mNsZTSAwUWRdXHwn3DQKvIV45LB2Wrx3f3LyeHUgRTvbho+mttjZLnC6tzACZTW3Wcn1G3ue/x8Sczi/NwXEsSR1vIM14rXkfRjgfnB0uMB0yTs+Up5iCm/fLUf/g1tjVOh/FzEOJ2vgmQMQDxKsrTZ+IwNk8yzu+J2U9YiLyuRp1/4/b1rVUme1aQU3yZWxbx7ioRAwlHZmBXAAur7dNNyu/GnFrU84sWaTHvNk1GwsaZ+xylceo/UAcqK2g/8LWR3GuZTJ2L1+R5veM62Yi+VLypN8jZ1iTcO1fLmYleK104wAIqjTpelCPnRDV2CwUI4ZW7ueJVr7u+tdUAs6TuT4BqJt1DvQ9ap4Fa68SBM15DZga6cqEAXGomfA9uN49SRKa16cyabQ0vqC7A3lQ5Osk1PcOM8WffPtarWhKVU5kP5IqOe8lWftuCosiAFfuAq62VO6Yb5wTz3l88NAPsSjEZkkz3pmpcIQwWUR0DkiOJOynnR6Fj4uMn1pWGrlPLvYz56+Tcm4OD5oOYqz2IYrZmXkBlrYG8k8Ax8pYjkAk7AqbrAletnUBjrlFgu1LIa1jN5/wFH3MgNf//MuUjgMjcj+xn4OKGpM+UmWgDYyNFTO0S5I5PBj5akEhj2k4Fdqmzat/uJ6tj/eaoq1fiJ81po6zbLzLev1tc+4JUxm36Ce9nqpSIcG+s58PJKD/tKEUqbz922yCFtQIlA+k1BBVO0QAmaltnYUzZrzKxnadAuTUckav4K5J6baagAes5bDLrK6vWZVx4QOn7lCfQoCBEuv0IROJmjZOy842aUDtZ/elYyzeRpDFDu8PtKI9iJxo0n6yknbuxUyD4Q322YSbA1zEbUWvG59pF35KM+jNQqliZ+RqsqekaaCkHTuu702wv4G91T+bHbMUYPyT4cCTdJmp9qH//wOKOIFiJK4JNiGNZAZRcwtJaUWh9ZuVgij8LzrUwu2X9q6+ELqq2409Uu76Rc4EydHvMdBClf58c05iPLuhdJnBqVPc6m/67hTxSSccFE4BwNvLU/KtCTRcbJcfPpjbcLueakN3SJb09OpYAZA8wxh4sAW/ETbA+1mtxcdiwo+GMJ2gi6igA31X1Hfb9BoUIWgS2a0eCf45t4hFki6wQpOsNJKa43AysU9q1+AEftziwgWoFpe2LTFwTcFiScQQPENYWtrrLy99SxF85gsIl4vD0/WRBSep/pFHzmpjTVfmbpE/hM56OuE/xoHSVe1cTb6wBFu81nERCE9O3yEnx/qljdTFkMXjT0e/+vFYw53IQ3sFtwaJr3lm1d2imh6P/iC8Fi1YPq1ARjf2WnWDfAnh3u8ZWp/N7tLM7J5tndBVQ3E7bf4u2UUjdjVMNhi8qerk599ukUgMVaGVw490RoSS5CRgBzzMNIrOgE2GRbIZ5tVvRQMUnNZFTqFmnHFBxdc+F5X/W95ghFyb3TPIGOp4L+M8/nGsa8EsApEgU4gsYtBqSWfJntQDdQaJMJWjhrANHrLXix1JSN1F5nPPh6TOVY1dg== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0d7faab7-cbef-46ae-ceca-08dc6b624517 X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 11:14:59.0925 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Tws8oIYOsK8q+1inhguB+BWXqv4bNPNo1LCyghpl8xMY3CnQ848v7stb16QyfOpMfqaf3WbvutAOpp3LAlE82oYQCkb4gip4BZ1v4jOqhiw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1238 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240503_041506_673189_2385521A X-CRM114-Status: GOOD ( 21.98 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add sys_gmac domain sub-driver. Signed-off-by: Alex Soo --- drivers/pinctrl/starfive/Kconfig | 12 +++ drivers/pinctrl/starfive/Makefile | 1 + .../pinctrl-starfive-jh8100-sys-gmac.c | 89 +++++++++++++++++++ .../starfive/pinctrl-starfive-jh8100.h | 4 + 4 files changed, 106 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-gmac.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index d78f161a636c..bc123c0bf35e 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -82,3 +82,15 @@ config PINCTRL_STARFIVE_JH8100_SYS_WEST This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JH8100_SYS_GMAC + tristate "StarFive JH8100 SoC System IOMUX-GMAC pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + depends on OF + select PINCTRL_STARFIVE_JH8100 + default ARCH_STARFIVE + help + Say yes here to support system iomux-gmac pin control on the StarFive JH8100 SoC. + This provides syscon registers to indicate voltage level on SDIO1/GMAC1, to indicate + GMAC1 pads voltage level under different GMAC interface modes, and to configure + GMAC1 interface slew rate. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index 784465157ae2..236a693a8aef 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100) += pinctrl-starfive-jh8100.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_EAST) += pinctrl-starfive-jh8100-sys-east.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_WEST) += pinctrl-starfive-jh8100-sys-west.o +obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_GMAC) += pinctrl-starfive-jh8100-sys-gmac.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-gmac.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-gmac.c new file mode 100644 index 000000000000..3758280e3660 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-gmac.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC sys gmac controller + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include +#include +#include +#include + +#include + +#include "pinctrl-starfive-jh8100.h" + +#define JH8100_SYS_G_GC_BASE -1 +#define JH8100_SYS_G_DOMAIN_NAME "jh8100-sys-gmac" + +#ifdef CONFIG_PM_SLEEP +static int jh8100_sys_gmac_pinctrl_suspend(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + sfp->jh8100_sys_gmac_regs[i] = readl_relaxed(sfp->base + (i * 4)); + + return pinctrl_force_sleep(sfp->pctl); +} + +static int jh8100_sys_gmac_pinctrl_resume(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + writel_relaxed(sfp->jh8100_sys_gmac_regs[i], sfp->base + (i * 4)); + + return pinctrl_force_default(sfp->pctl); +} +#endif + +static SIMPLE_DEV_PM_OPS(jh8100_sys_gmac_pinctrl_dev_pm_ops, + jh8100_sys_gmac_pinctrl_suspend, + jh8100_sys_gmac_pinctrl_resume); + +static const struct jh8100_pinctrl_domain_info jh8100_sys_gmac_pinctrl_info = { + .ngpios = JH8100_SYS_G_NGPIO, + .gc_base = JH8100_SYS_G_GC_BASE, + .name = JH8100_SYS_G_DOMAIN_NAME, + .nregs = JH8100_SYS_G_REG_NUM, +}; + +static const struct of_device_id jh8100_sys_gmac_pinctrl_of_match[] = { + { + .compatible = "starfive,jh8100-sys-pinctrl-gmac", + .data = &jh8100_sys_gmac_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh8100_sys_gmac_pinctrl_of_match); + +static struct platform_driver jh8100_sys_gmac_pinctrl_driver = { + .probe = jh8100_pinctrl_probe, + .driver = { + .name = "starfive-jh8100-sys-pinctrl-gmac", +#ifdef CONFIG_PM_SLEEP + .pm = &jh8100_sys_gmac_pinctrl_dev_pm_ops, +#endif + .of_match_table = jh8100_sys_gmac_pinctrl_of_match, + }, +}; +module_platform_driver(jh8100_sys_gmac_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JH8100 SoC sys gmac controller"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h index 7c7a05c1c828..90eef6417dd7 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h @@ -14,12 +14,15 @@ #define JH8100_SYS_W_DOMAIN_NAME "jh8100-sys-west" #define JH8100_SYS_E_DOMAIN_NAME "jh8100-sys-east" +#define JH8100_SYS_G_DOMAIN_NAME "jh8100-sys-gmac" #define JH8100_SYS_W_NGPIO 16 #define JH8100_SYS_E_NGPIO 48 +#define JH8100_SYS_G_NGPIO 0 #define JH8100_SYS_W_REG_NUM 44 #define JH8100_SYS_E_REG_NUM 116 +#define JH8100_SYS_G_REG_NUM 19 #define JH8100_SYS_W_GPO_PDA_00_15_CFG 0x074 #define JH8100_SYS_E_GPO_PDA_00_47_CFG 0x114 @@ -36,6 +39,7 @@ struct jh8100_pinctrl { const struct jh8100_pinctrl_domain_info *info; unsigned int jh8100_sys_west_regs[JH8100_SYS_W_REG_NUM]; unsigned int jh8100_sys_east_regs[JH8100_SYS_E_REG_NUM]; + unsigned int jh8100_sys_gmac_regs[JH8100_SYS_G_REG_NUM]; /* wakeup */ struct irq_domain *irq_domain; struct gpio_desc *wakeup_gpio; From patchwork Fri May 3 11:14:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuklin Soo X-Patchwork-Id: 13652674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C1C2C4345F for ; Fri, 3 May 2024 11:15:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iBVWfSo72Mvms2EGtYcODGqPs/ELAh94rWDn3yu/nFM=; b=xHLLLC2tDbRQNy ffVBhqmjlzNzHc0Rqlh17550CevVmMSP6EVxuIJfJXLVaA7X8SEYBfgvXu/tlfXs8/heUFdlOAnWL rtgmLi8SyJnptZJR0oTzfK0Q+yM8FqBVsEVSPBzSI3O0PirGV/3uURPefdaDnq7Nd1XoUS9dh3IJD s660G4Vt4sBIXv8FZkShyOMmuHfFW7wS9gm+aRQ9TDgJBWRVYG3H6l8+HoxtSpVzXAvktht8haAbl 6J65aAK2WdEIsXD33QhVpnRVhfn4U+dcVJ9KuM8HVLWdK7BYfSt190U7eihQ3IQcQIad8pI/3RBgM TIB11Xm/nRE2wOD1InYg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qsi-0000000GD58-3Qca; Fri, 03 May 2024 11:15:12 +0000 Received: from mail-bjschn02on20717.outbound.protection.partner.outlook.cn ([2406:e500:4440:2::717] helo=CHN02-BJS-obe.outbound.protection.partner.outlook.cn) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qsg-0000000GD1s-0nj2 for linux-riscv@lists.infradead.org; Fri, 03 May 2024 11:15:11 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hOfVsAfc7nWM6u/SwH4u7Se92McExawo/Apc/+YgxyNXLTGVtVV0IbEcdGhPkebvWTVAsETNBH9Zi5PTTRkkwdYIJvhkeC90MGk8p2f/8BhS8jLYDUGZ2+bPVWh7/WcqFoLnpfkv4rQr5MmbTIuCoCOmnhEyLrlf9JToYgMOBXUt1yCgZhmDBgRULUpMZrgHZVxgie7KI7zHvMotJajtLojtr3KwcB6PkrNQyYWQQgntk4tDQwMOROJrzFPTD1wWpqwgdBLtnZG3Gfs47cDfj7vkckBhGvIZS3+7omihK2eeWth9ny31hdPi/sQYMPklnQ8zribMdZvGR+hJJhu2DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hRmGvKORfU/XNM9dcs5jbKFZWA/+xM+i3RYFCRfhR8A=; b=h3QT0+/wVCBpYUfyO/sLXivts2SRVGwO5V2FY6Z2mWoC+7xZSh4wTJPXMX5FlHiZOsL67xEMFCx9Gbnnw/T26anrgHAMGVwqGuRdAow8LeG7zFE1us2pR4VVxsBNkbuUix3TcSgf3f3K8heo/kGrH8h6ls6VUTNCdnDbwMecsf5EE1hNmZN4XQ1GQx7sMriRecdnpE6le9JFJIi8NrwJVyLWxIFaZuNWm2GFmC4yjuVp0lEuHoQXyIV/yE4tHp9GpSmSqWjOkHmNuPh72+ePVIsf1fYGl78UphLnNnLivv37S+8+5mbPhbfrEQgOu1qvIS/z2kIQWfMVzWr7OW0dzQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) by ZQ0PR01MB1112.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:c::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Fri, 3 May 2024 11:15:02 +0000 Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4]) by ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4%5]) with mapi id 15.20.7472.044; Fri, 3 May 2024 11:15:02 +0000 From: Alex Soo To: Linus Walleij , Bartosz Golaszewski , Hal Feng , Ley Foon Tan , Jianlong Huang , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alex Soo Subject: [RFC PATCH v3 5/7] pinctrl: starfive: jh8100: add AON domain sub-driver Date: Fri, 3 May 2024 19:14:34 +0800 Message-Id: <20240503111436.113089-6-yuklin.soo@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240503111436.113089-1-yuklin.soo@starfivetech.com> References: <20240503111436.113089-1-yuklin.soo@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0011.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::20) To ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1176:EE_|ZQ0PR01MB1112:EE_ X-MS-Office365-Filtering-Correlation-Id: 72b0325c-23a4-4bdc-20ea-08dc6b62470e X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: X9XHUFvjvhaFrx9b1VcK9CCvqUJvzKInpgbw40dfutbGhmGf/o6x9lxIpsobuccLh87CtLjyPQsGzjHwaQz72pGAyv7y/uQlegAeG8l1OilUVhF8NkURAk521kq8o8ef+4nBIYhIndhuVlKvYqZmByO/HXgwRazjmtgAQM2YGUdwQwJdPCZoRO0j0Eby3kXbki89FjD+32mGjjayJyAq76a6eehuzG2ZtTM1tqqy/1GBXFEHCuemNZFFnhRAl3ou8P57ZckxpK+4IwKC9BxB5FUCTGHgp9Wyt7VwbTMIvjoj9PKl7EX9YvSiXKwWbMgzhr7YXhse02kzfodrcIWnrpkcjV9rd7B8do2wJaPYHaDFv8p1hR6gs+QtVgoapwhhd19XR1tg8i9rGCLFK2TgZXVUn31s+W3t9sAp6PHX9xqAcGdRMlUYzcaDUSHP1bU/ywCSrSIuTLY8JoKE/C3XvDUNXeyLZrS5EVsszuqEEDCbnQnwRzctyf+fnvJZE0KyCcrbJXGbHklJXyHjXd1k6MKv988dQHCgrxWmCQnkeVnH6WYgKjUZY8BwuxcaJzmUUEgx5PZ116c2+AYFzMjsBkvsgrE+6hwmPMboXrWnB0BUuv4Nu/sGJZrNBCtIuCOfZtmmTNnGSx/ODKKopMiOHw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230031)(41320700004)(7416005)(1800799015)(52116005)(366007)(38350700005)(921011);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: EN12XgU1YNF2kJXW54i2HE1IzxuJmjyf3EMNyY4HRLkMHHflnezfrpLoqVRzGuETS24g4TO/a4Yl9dtcpQO9tx4UkB3AxV6N0VsCDE/s+j34WpSQkEvROhBH/rNyt8lRjuEaUYYOVfekhshN8ZkgH4D86/TCEQw4uvV0beu0jBhZ1jdsBUyAiOtYLWzqDLM8rF6OQN6nwrcO7Zmu/wuzjSpiNxSiQmtoBOoVERdhOiL+n7NPVRi6HfjlRfnkKJCEi6aJa1p4VgYNXniLbFPxqB23f8K8K3L7OPGjG41gxO6JWiV9/n+DVGsawDVuK9eMst2pp+Rp3jPB1Q+JPk+8KFg3HlrQswSO/4lTN1Cb91QqyCrVVELCIT1YiQiIlFwVfDe1Yc/Vi9kfGV3pXAcgDGEsWlCsxXlnYBh2hqLGy5gWiEC54q008x12H2Qtn4CVJqKJhfxo/2kz9g8lZxImxuuQiYCM0p4LC1pM60fBMW0EfTRfzQaTBj+2bDRJfld2EI1CWKCDwaesX/WXSwJcAPbYGUaZLt5s4eZ74Bbwry0EXYGfEpJtO4BxCOBtISn4qEvOlvha0BgkjjnkGhEMg53UvxK9P070W7tX/Y8DL+NM237ukSVYfWzO4+NKDNyrT1wm6zGHQzkkO1f597QRfFW8puDUNrtFzIYhmkcsmWWtsRX+uKLjULeCx/bPT4qpZ9TcnY7we3jEBc12GDkOt6nCtWksv1UncG8chKfs4MsYaDMLva2gmMNkDzX2UElIFcu0RSCSFKubllujV6QBbOgBZCkFIppFqJC/zaAWIgpjyG1ANeRh+LqF80zssQL8GaDmnSjzMCmMy4v/3OMC4FcsE6X1Zm36zFha8HlYRb6pOJinDJjv94Zaie4l8XuY2+EjHRYcwzUJXpJ2NXBsqE4WY4RG9ugeEaqLYdcKc1p5VvxwwYGjVNHwTWvPTj0g3lIEZN2haTRTXLa/USvC4mig5ztdU8qMdTS7kCHMsrWwc74FtI04M1yJAwb8mMCO8jXgbiJjL1qCH9kfn1AAymRmhFbEp6aokBPUpQRxKEmQtuzrmKKPHlXORpSub37rTlZChAtcvMRzzzVnKG7iSlZYueFREewnUInW059KDmBxf/C/9v/8AgDRCemwBFFOFRuynHyUiAfZupxmC7FphNb7jYQF9jDGdNVwHYQWVTPbkfk6zYVP3YPcLKu58tg38CJ433pTdmLlGqTjIXsHsBG0QCj0l91hQVDzSvfFXUt6V1VazaXG8TkiaphNMp9hYBGIXzbVyxg2Qz9iJYBENtZuWQl7KcuIp5UFgU2bIgQTxEqO6Cmrno8/MIUs1kCx1Wuj3KrqEOSyl3kMt++HnPHtWXKlb8ClVC7lnAQ6k4G2PuVcghZ89xXo+bXE7yNqR5AjTiftWDkZr8BK80nImEKratgE4/fOPH1Fa01oirWNkvoO/5bLEhT1+aS2bnzqUq+wxkgKJsLnNqwj8DwAW0LuMY9H6WCsfOhunIjO1PQSQhI/HxKSuodo/82o92kghGcBVHemUazXR1p6O5BDd7OtQtA3S3Lxx4XXViMg32b7FyR6q17IEHGwEsVbJ8z0I2NVtC+3hwgyf2OgMtxtnw== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 72b0325c-23a4-4bdc-20ea-08dc6b62470e X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 11:15:02.3764 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7g6MGipZWrQpyuMDpTI6Joid6tA1vWrze5R7jfLwlmh3h5wJhiGlQaCZJBv8qzNveRpZq/arml4fWMIND6a2JFHeSQEoXuIMjvDhuVowbBE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1112 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240503_041510_486825_44CF5248 X-CRM114-Status: GOOD ( 22.55 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add AON domain sub-driver. Signed-off-by: Alex Soo --- MAINTAINERS | 7 + drivers/pinctrl/starfive/Kconfig | 14 ++ drivers/pinctrl/starfive/Makefile | 1 + .../starfive/pinctrl-starfive-jh8100-aon.c | 150 ++++++++++++++++++ .../starfive/pinctrl-starfive-jh8100.c | 3 + .../starfive/pinctrl-starfive-jh8100.h | 5 + 6 files changed, 180 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100-aon.c diff --git a/MAINTAINERS b/MAINTAINERS index dbd104f1f267..3f6b17688ac8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21125,6 +21125,13 @@ S: Maintained F: drivers/reset/starfive/reset-starfive-jh81* F: include/dt-bindings/reset/starfive?jh81*.h +STARFIVE JH8100 PINCTRL DRIVERS +M: Alex Soo +S: Supported +F: Documentation/devicetree/bindings/pinctrl/starfive,jh81*.yaml +F: drivers/pinctrl/starfive/pinctrl-starfive-jh81* +F: include/dt-bindings/pinctrl/starfive,jh8100-pinctrl.h + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index bc123c0bf35e..6c448837f5f6 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -94,3 +94,17 @@ config PINCTRL_STARFIVE_JH8100_SYS_GMAC This provides syscon registers to indicate voltage level on SDIO1/GMAC1, to indicate GMAC1 pads voltage level under different GMAC interface modes, and to configure GMAC1 interface slew rate. + +config PINCTRL_STARFIVE_JH8100_AON + tristate "Always-on pinctrl and GPIO driver for the StarFive JH8100 SoC" + depends on ARCH_STARFIVE || COMPILE_TEST + depends on OF + select PINCTRL_STARFIVE_JH8100 + default ARCH_STARFIVE + help + Say yes here to support always-on pin control on the StarFive JH8100 SoC. + This provides an interface to the RGPIO pins not used by other peripherals + supporting inputs, outputs, configuring pull-up/pull-down and interrupts + on input changes. And also, the syscon registers to indicate voltage level + on eMMC/SDIO0/XSPI/RGPIOs/GMAC0, to indicate GMAC0 pads voltage level under + different GMAC interface modes, and to configure GMAC0 interface slew rate. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index 236a693a8aef..46b1ab97779b 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH8100) += pinctrl-starfive-jh8100.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_EAST) += pinctrl-starfive-jh8100-sys-east.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_WEST) += pinctrl-starfive-jh8100-sys-west.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_GMAC) += pinctrl-starfive-jh8100-sys-gmac.o +obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_AON) += pinctrl-starfive-jh8100-aon.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-aon.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-aon.c new file mode 100644 index 000000000000..3ced9f94f47a --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-aon.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC aon controller + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include +#include +#include +#include + +#include + +#include "pinctrl-starfive-jh8100.h" + +#define JH8100_AON_GC_BASE 64 + +/* registers */ +#define JH8100_AON_DOEN 0x00 +#define JH8100_AON_DOUT 0x10 +#define JH8100_AON_GPI 0x20 +#define JH8100_AON_GPIOIN 0x54 + +#define JH8100_AON_GPIOEN 0x34 +#define JH8100_AON_GPIOIS 0x38 +#define JH8100_AON_GPIOIC 0x3c +#define JH8100_AON_GPIOIBE 0x40 +#define JH8100_AON_GPIOIEV 0x44 +#define JH8100_AON_GPIOIE 0x48 +#define JH8100_AON_GPIORIS 0x4c +#define JH8100_AON_GPIOMIS 0x50 + +static const struct pinctrl_pin_desc jh8100_aon_pins[] = { + PINCTRL_PIN(0, "AON_RGPIO0"), + PINCTRL_PIN(1, "AON_RGPIO1"), + PINCTRL_PIN(2, "AON_RGPIO2"), + PINCTRL_PIN(3, "AON_RGPIO3"), + PINCTRL_PIN(4, "AON_RGPIO4"), + PINCTRL_PIN(5, "AON_RGPIO5"), + PINCTRL_PIN(6, "AON_RGPIO6"), + PINCTRL_PIN(7, "AON_RGPIO7"), + PINCTRL_PIN(8, "AON_RGPIO8"), + PINCTRL_PIN(9, "AON_RGPIO9"), + PINCTRL_PIN(10, "AON_RGPIO10"), + PINCTRL_PIN(11, "AON_RGPIO11"), + PINCTRL_PIN(12, "AON_RGPIO12"), + PINCTRL_PIN(13, "AON_RGPIO13"), + PINCTRL_PIN(14, "AON_RGPIO14"), + PINCTRL_PIN(15, "AON_RGPIO15"), +}; + +#ifdef CONFIG_PM_SLEEP +static int jh8100_aon_pinctrl_suspend(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + if (device_may_wakeup(dev)) + enable_irq_wake(sfp->wakeup_irq); + + for (i = 0; i < sfp->info->nregs; i++) + sfp->jh8100_aon_regs[i] = readl_relaxed(sfp->base + (i * 4)); + + return pinctrl_force_sleep(sfp->pctl); +} + +static int jh8100_aon_pinctrl_resume(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + if (device_may_wakeup(dev)) + disable_irq_wake(sfp->wakeup_irq); + + for (i = 0; i < sfp->info->nregs; i++) + writel_relaxed(sfp->jh8100_aon_regs[i], sfp->base + (i * 4)); + + return pinctrl_force_default(sfp->pctl); +} +#endif + +static SIMPLE_DEV_PM_OPS(jh8100_aon_pinctrl_dev_pm_ops, + jh8100_aon_pinctrl_suspend, + jh8100_aon_pinctrl_resume); + +static const struct jh8100_gpio_irq_reg jh8100_aon_irq_reg = { + .is_reg_base = JH8100_AON_GPIOIS, + .ic_reg_base = JH8100_AON_GPIOIC, + .ibe_reg_base = JH8100_AON_GPIOIBE, + .iev_reg_base = JH8100_AON_GPIOIEV, + .ie_reg_base = JH8100_AON_GPIOIE, + .ris_reg_base = JH8100_AON_GPIORIS, + .mis_reg_base = JH8100_AON_GPIOMIS, + .ien_reg_base = JH8100_AON_GPIOEN, +}; + +static const struct jh8100_pinctrl_domain_info jh8100_aon_pinctrl_info = { + .pins = jh8100_aon_pins, + .npins = ARRAY_SIZE(jh8100_aon_pins), + .ngpios = JH8100_AON_NGPIO, + .gc_base = JH8100_AON_GC_BASE, + .name = JH8100_AON_DOMAIN_NAME, + .nregs = JH8100_AON_REG_NUM, + .dout_reg_base = JH8100_AON_DOUT, + .dout_mask = GENMASK(4, 0), + .doen_reg_base = JH8100_AON_DOEN, + .doen_mask = GENMASK(2, 0), + .gpi_reg_base = JH8100_AON_GPI, + .gpi_mask = GENMASK(4, 0), + .gpioin_reg_base = JH8100_AON_GPIOIN, + .irq_reg = &jh8100_aon_irq_reg, + .mis_pin_num = JH8100_AON_NGPIO +}; + +static const struct of_device_id jh8100_aon_pinctrl_of_match[] = { + { + .compatible = "starfive,jh8100-aon-pinctrl", + .data = &jh8100_aon_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh8100_aon_pinctrl_of_match); + +static struct platform_driver jh8100_aon_pinctrl_driver = { + .probe = jh8100_pinctrl_probe, + .driver = { + .name = "starfive-jh8100-aon-pinctrl", +#ifdef CONFIG_PM_SLEEP + .pm = &jh8100_aon_pinctrl_dev_pm_ops, +#endif + .of_match_table = jh8100_aon_pinctrl_of_match, + }, +}; +module_platform_driver(jh8100_aon_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JH8100 SoC aon controller"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c index 8c3e4a90d68d..edf2a6fb6da2 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c @@ -416,6 +416,9 @@ static int jh8100_get_padcfg_base(struct jh8100_pinctrl *sfp, } else if (!strcmp(sfp->info->name, JH8100_SYS_W_DOMAIN_NAME)) { if (pin < JH8100_SYS_W_NGPIO) return JH8100_SYS_W_GPO_PDA_00_15_CFG; + } else if (!strcmp(sfp->info->name, JH8100_AON_DOMAIN_NAME)) { + if (pin < JH8100_AON_NGPIO) + return JH8100_AON_GPO_PDA_00_15_CFG; } return -ENXIO; diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h index 90eef6417dd7..ba44a7dd96e1 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h @@ -15,17 +15,21 @@ #define JH8100_SYS_W_DOMAIN_NAME "jh8100-sys-west" #define JH8100_SYS_E_DOMAIN_NAME "jh8100-sys-east" #define JH8100_SYS_G_DOMAIN_NAME "jh8100-sys-gmac" +#define JH8100_AON_DOMAIN_NAME "jh8100-aon" #define JH8100_SYS_W_NGPIO 16 #define JH8100_SYS_E_NGPIO 48 #define JH8100_SYS_G_NGPIO 0 +#define JH8100_AON_NGPIO 16 #define JH8100_SYS_W_REG_NUM 44 #define JH8100_SYS_E_REG_NUM 116 #define JH8100_SYS_G_REG_NUM 19 +#define JH8100_AON_REG_NUM 65 #define JH8100_SYS_W_GPO_PDA_00_15_CFG 0x074 #define JH8100_SYS_E_GPO_PDA_00_47_CFG 0x114 +#define JH8100_AON_GPO_PDA_00_15_CFG 0x90 struct jh8100_pinctrl { struct device *dev; @@ -40,6 +44,7 @@ struct jh8100_pinctrl { unsigned int jh8100_sys_west_regs[JH8100_SYS_W_REG_NUM]; unsigned int jh8100_sys_east_regs[JH8100_SYS_E_REG_NUM]; unsigned int jh8100_sys_gmac_regs[JH8100_SYS_G_REG_NUM]; + unsigned int jh8100_aon_regs[JH8100_AON_REG_NUM]; /* wakeup */ struct irq_domain *irq_domain; struct gpio_desc *wakeup_gpio; From patchwork Fri May 3 11:14:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuklin Soo X-Patchwork-Id: 13652673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7B20C25B5C for ; Fri, 3 May 2024 11:15:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fBrStSmAIJIuH+5OqJhrzDuazASAzgbF/YySPP66o/I=; b=ofWc25548lElUJ /Vxp1NgABE5TcyrwMzKGhNbTYVTHOB6hm0orx82W1tkhaeWe9CDcFPof99rgkYLwR6InVEr+yuxrX B4RB+xigx4P1fKHJs4wRg5Ds1Ssybtr1+bMqqE5mboipBYMR8IucL7iuWV0DUzpbH8tzCvbM0QVN7 jdV9xrHC1bM9L+3FOQtu1Js00z/NBL3Nk/l6Tx956dPzTAq1OHKbn2Nj/a7g1n3PRFmMVrRZij09/ 6h+vtpXGjqNr5Lxax02Tr3WjlHOLmjAHWmKsqdsH6YvV3nf+HN+L69K8PGBThUdyGXK9XsEKGaGZM +TiZPCH2HsG9fEKKR0IQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qsk-0000000GD6b-3T8C; Fri, 03 May 2024 11:15:14 +0000 Received: from mail-bjschn02on20717.outbound.protection.partner.outlook.cn ([2406:e500:4440:2::717] helo=CHN02-BJS-obe.outbound.protection.partner.outlook.cn) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qsi-0000000GD1s-1Mlm for linux-riscv@lists.infradead.org; Fri, 03 May 2024 11:15:13 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jlvKIViyg9sKWJP0+CRNaCxzGcvSOOhH8NtoTjv+vOl926zjllICY+B/RzKC+fkGMU+d26CgHXG6yyD88yaSOpPBMPzv7C8Jx5zqXBB8K6YXyb/cWB95txm2GdNOP/jbFCLuJr80eiBWVlv25/Co5jClE04hmmtg9hBgS+vWBPcBjbbAYe770DcEJgly77Rt2EEeS/02Q9DGlgHjICxZaOzS6NCbdJ16tl0A68vu+erAR7jHdH/hobmHv3yP/J+3UVFrWwATZppwUdgW9rg9XT84e4OEEvNjGZH2V22OOlCkscyfq12nINB39QHT5k+SaTO6vhBasjbdBSeWYKXnwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dAqNpNO+pzoUOb1ovcRYsgkdv6JzCxdG9bEgFv6/p0Q=; b=bkKIM/sjjQRILtyCzWH/GJsjqaDWCrSlwzP4lpcBGxN6pzaK0wlsTBki9OTKHXjsz0OQ92ba39eT/oJrbaIFbg9JPMkx30ALRMujsb0rZyaxMJPPefJ5Rq38Fc2z9FW2on26XkT/7nfASNrlmoOEfbS58fSWgnoGbd+belxqJZV7CONEiqBDyujWjb3St0KRgFCCha2fmftZwdchqtisBujKJ7PUMj6H3PntCuP2mTZM7YkD7yxOQhtmS5OtYXVMmhwd0GEZyYwTxQaxs99rS++m1/ri52dEUCN/C/FctIpLypGF+enI6oJ28VNmYGJebqLESUTF1MFfFyrm/EiJAA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) by ZQ0PR01MB1112.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:c::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Fri, 3 May 2024 11:15:05 +0000 Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4]) by ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4%5]) with mapi id 15.20.7472.044; Fri, 3 May 2024 11:15:05 +0000 From: Alex Soo To: Linus Walleij , Bartosz Golaszewski , Hal Feng , Ley Foon Tan , Jianlong Huang , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alex Soo Subject: [RFC PATCH v3 6/7] gpiolib: enable GPIO interrupt to wake up a system from sleep Date: Fri, 3 May 2024 19:14:35 +0800 Message-Id: <20240503111436.113089-7-yuklin.soo@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240503111436.113089-1-yuklin.soo@starfivetech.com> References: <20240503111436.113089-1-yuklin.soo@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0011.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::20) To ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1176:EE_|ZQ0PR01MB1112:EE_ X-MS-Office365-Filtering-Correlation-Id: ebce3d29-f0be-4031-fc78-08dc6b6248d4 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NwHDAIU/Y9PYmIoVj46oSiFQgBksWJK4YZtdts3CQ10zkRJD3XTKUbVcLlC6G4cfouyTMFgiOrZ1Vjq2m40MPjFpjJNg4Xj1cOZsD8yMmvrPcEtpe/pbFq9RbREUf62RuiZgjV/7bcqTm8AylumF1H9Hxt+4PlLZxudMyRfte2UgHSLxUwAVEdpOBtGKS10UTLWJuvHP5v/80JQpfOdEsy5C2/nDImWD9Cqm9PPds9yIO4zFkkxmoxDw7nOze8vf5vi0KBjrIcKr4MgAve/eVsio6FNnsO64yrMnLzFO2LMv9YsSCPWfA4/Bil83J3Db6MLBH3jyortkiKQOg+6MUztqX9Xfnuc2uVwqzpYdhfcrgG+L49hszZP/7klJe4VeN31gPi/QpYZ6p8uIEAwYhJgOoAUrqxxAulIdtBHTDEbkovN7d7D6iJAvtS12+vsP1oqrqhqQGdHqx1+tDo/xpI7pWkTe4fJ3Vv/+h+aoE6m7jPBkYw5nNMSXJekQf7zWlvRzALHpYSZLeotF5oTutMUBMXWL2+ANhvCzFXFn3IR3PjbJf/S0apkjJhRxqwTU3xR1b8a227U9bnBTqHdhORVMHmPs+yxXtIwcg0aPsKFBlqRhWVG9IAufMu6oQ7rUnC9dwRz5uswwArTu7UjUKA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230031)(41320700004)(7416005)(1800799015)(52116005)(366007)(38350700005)(921011);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wUFH8X3wJl+3Y78oXno3rgnp0IZbQUjiD5Es4WWqSM7fr6XYhKh8BTnubT0jIsq/NofV54V6B+ti1CTB+q1yzd7LdcGtHVBkk+vqXLPhwpqF/f65WEqmF6n2cM5deJXLuPjSPYk+CFNR8Cams0vjLsemmYP6C6Mcr4kc0ZyynPDnnOxCLPfv5CVhhzxuNOBNv35Y1fo1RYLJxzgKf0x5QtLDyFwotunYvWDeJHgDDloZEo08ZJeCd+JlTc+KCuHOUrhuQJG3r+wGqvkisWEV7yHW5lLfJUPcJFWz05NArIhlp/AbvDaYRNlrT6vvL4GakCWC3k1jKtxbHRaSbaYnQdVRFwj8gbZDbNu1fzVYRDOP7tAEjVlv5KRMmtCPIKPTxng9a91pRaClEndcez01tpenugAUJFFQAaTcmP+53xlaBXAfvPuAlsmDeHv08YArhB9Ms7qSLI8GNZrvv6pzClkmxge79fSzWGsBMHDhKHlO5HkrH6ZGD5hdENR4uzV7MNpvZmb5/VFmH1vCVx4LGN3hyfKv2BPobKterJcun8/1vmyhuLabfp92YNIGvJSAgVwbCdtEFUmQMLmSl2B860luVF8FqlMaMTVSonXD9n/+nfC+xSJvDcY8Rqg5vE23RNsuGJ2Cf6BjqzfHGDJ/uXA7ptwzYgvfqIoHZnqbDP1iCl84CB8GEikN1OBWouUa8B2UjcUqYsMJkR8xgGBtCf4T49t+rgVALqI98SaqXVRsI7j04JTi6OxCc8Z7GgQAZ6S3L5h3SRnWEt7hiwU6TY/nxmdp7DZmEMwXj56AyKu5yhBm1TxDE1U3mmeDP+wiLSxvenFjfzOwzHkAbIlaDhqJKiVn8m74gH0lAkPc+EC/PNQJClUE8tIS1NjDr7Y+H3quea8p3g9Q+TDE0mc8T/VIjUFaqrH0G5zW3ILyKHeOHZsJc62O6gN2ZaGJ44YN2Zk+DI8ehYZCkzuLTrkvEulaVzBzINY8sOkCChOp2O7OCC98GD+rzrczj9/WP9agKYqFvOqCbdk8wHTLyAQsBzOvHI55xwkfdHr22b6Armh7bcgspo1YFVQpNfiy7c9jQthkPLptrfBLn/z9RluiEO4UPgKkwwK3PjZQ3QF9zEi+mh2kglcltf6GxT0qtczgmt5iayJGqj/TjeOK/whmmkTY88KmCPhIdB7obMJ+2rPKxp1W0C1jKB25bcbzHWQExbizRiUgtH5BuZ8U9o3SDjKNGMdE/w23P7U8HQpI9z5hTzhxA8XjRJatEm0nfh12mJtbcymJUwCIR7JQRd4Wx/U/VQMTrFywJHDFct+JKU1O+YWknnUJf0dmOjoMr5Du++pO2E7jBMBAlfPjU+7hXecv5YSIBqvxViUNynii4bQltLzEsULIQpB4UNKKf8oSg4+bX1JE47H5PB2xh1FfryToNzW1lTQepGKtGE4lXLj7ldIWFUGTwBXdBJwSLUCkJtkeytSQUN9SojG7dJb8/HLVoFeqOYWqAupfn6aIeHfnkTiYxccTrAEDFIqeFBNPGU79FmYVSCmt3beV5eBEsMbOfBLxcZ0Gf7rM5JOd/0C0t2TU+x7u8S1rbA1CQOM7Fti4k1zQh/7vnLZxBYmwYw== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: ebce3d29-f0be-4031-fc78-08dc6b6248d4 X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 11:15:05.3566 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: uwz7IU8b1Bb22q5T70iUIpLHoGS8688VTJYSP68RbPJHTsoLKTHScN3l/mZf5lEGTZyMsPk1Cbmlu4cQlvjdC1Tkrq9sEZtT5t72H+ZOB6U= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1112 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240503_041512_416549_46FE218E X-CRM114-Status: GOOD ( 16.20 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add function gpiochip_wakeup_irq_setup() to configure and enable a GPIO pin with interrupt wakeup capability according to user-defined wakeup-gpios property in the device tree. Interrupt generated by toggling the logic level (rising/falling edge) on the specified GPIO pin can wake up a system from sleep mode. Signed-off-by: Alex Soo --- drivers/gpio/gpiolib.c | 87 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 94903fc1c145..92cfbc34abb0 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -96,6 +97,7 @@ static void gpiochip_irqchip_remove(struct gpio_chip *gc); static int gpiochip_irqchip_init_hw(struct gpio_chip *gc); static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gc); static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gc); +static int gpiochip_wakeup_irq_setup(struct gpio_chip *gc); static bool gpiolib_initialized; @@ -1045,8 +1047,15 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data, if (ret) goto err_remove_irqchip; } + + ret = gpiochip_wakeup_irq_setup(gc); + if (ret) + goto err_remove_device; + return 0; +err_remove_device: + gcdev_unregister(gdev); err_remove_irqchip: gpiochip_irqchip_remove(gc); err_remove_irqchip_mask: @@ -1874,6 +1883,84 @@ static int gpiochip_irqchip_add_allocated_domain(struct gpio_chip *gc, return 0; } +static irqreturn_t gpio_wake_irq_handler(int irq, void *data) +{ + struct irq_data *irq_data = data; + + if (!irq_data || irq != irq_data->irq) + return IRQ_NONE; + + return IRQ_HANDLED; +} + +static int gpiochip_wakeup_irq_setup(struct gpio_chip *gc) +{ + struct device *dev = gc->parent; + struct gpio_irq_chip *girq = &gc->irq; + struct gpio_desc *wakeup_gpiod; + struct irq_desc *wakeup_irqd; + struct irq_domain *irq_domain; + struct irq_data *irq_data; + unsigned int offset; + int wakeup_irq; + int ret; + + if (!(device_property_read_bool(dev, "wakeup-source"))) + return 0; + + irq_domain = girq->domain; + + if (!irq_domain) { + dev_err(dev, "Couldn't allocate IRQ domain\n"); + return -ENXIO; + } + + wakeup_gpiod = devm_gpiod_get_optional(dev, "wakeup", GPIOD_IN); + + if (IS_ERR(wakeup_gpiod)) { + dev_err(dev, "invalid wakeup gpio: %lu\n", PTR_ERR(wakeup_gpiod)); + return PTR_ERR(wakeup_gpiod); + } + if (!wakeup_gpiod) { + dev_dbg(dev, "property wakeup-gpios is not defined\n"); + return 0; + } + + offset = gpio_chip_hwgpio(wakeup_gpiod); + wakeup_irq = gpiod_to_irq(wakeup_gpiod); + if (wakeup_irq < 0) { + dev_err(dev, "failed to convert wakeup GPIO to IRQ\n"); + return wakeup_irq; + } + irq_domain->ops->map(irq_domain, wakeup_irq, offset); + wakeup_irqd = irq_to_desc(wakeup_irq); + irq_data = irq_get_irq_data(wakeup_irq); + girq->handler = handle_edge_irq; + + if (!(wakeup_irqd->status_use_accessors & IRQ_NOREQUEST)) { + device_init_wakeup(dev, 1); + ret = devm_request_threaded_irq(dev, wakeup_irq, NULL, + gpio_wake_irq_handler, + IRQF_TRIGGER_FALLING | + IRQF_TRIGGER_RISING | + IRQF_ONESHOT | + IRQF_SHARED, + "pm-wakeup-gpio", irq_data); + if (ret) { + dev_err(dev, "unable to request wakeup IRQ: %d\n", ret); + return ret; + } + } + + ret = dev_pm_set_wake_irq(dev, wakeup_irq); + if (ret) { + dev_err(dev, "failed to enable gpio irq wake\n"); + return ret; + } + + return 0; +} + /** * gpiochip_add_irqchip() - adds an IRQ chip to a GPIO chip * @gc: the GPIO chip to add the IRQ chip to From patchwork Fri May 3 11:14:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuklin Soo X-Patchwork-Id: 13652675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CDE4C10F16 for ; Fri, 3 May 2024 11:15:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Gl2MxlTba8Kf4NfgXrk2r/DqcvLV0gLRcMbszp+CpBs=; b=BxikVloexlApEm gvy7MBlI5WnkeeCNjwXRr7rtcPYMrUd6PPyjGuCvIw9Dp2iOvy1MoUbfzpFmOv52Kwm/dpw7kQ7OP /dn8gxkkVhr6y0WM+L0qLLvk7hH1aQHQTdmVpjElrwaJ5WEQ6uiB8AWx4MRKmiFNf6Tkd95YKsgg8 oL3ZH9x4KzwWXy3eDyJwjDMTNZwp7ACCvCowUanr7pEh0ryz2yvQ9xsCoGgMMkboWOQxTOKkWVnsb 44glOS4SLqFvnoFsOozwC7HXV3x9xaq+DP7bk+YZzyrY9VNEy38ExR4Nv7q2bi1Cl8FdlwdCMTR2m qIIMuMjlfYZ/F9U/sXFw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qso-0000000GD8V-12u1; Fri, 03 May 2024 11:15:18 +0000 Received: from mail-bjschn02on20717.outbound.protection.partner.outlook.cn ([2406:e500:4440:2::717] helo=CHN02-BJS-obe.outbound.protection.partner.outlook.cn) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2qsk-0000000GD1s-0ITJ for linux-riscv@lists.infradead.org; Fri, 03 May 2024 11:15:16 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CtSHT/InoSCjVucKDoeA2lvghwmBF1dhmokZT8CL4CZc3kK7SPXM3xw2Yx1XNXBGV154Wteh3CBDWWb9u27cx5AufiKNJX5jmZswA1awSd7B+mjFAnhiLdmDUaJ6k1k8Yde145SPqYte0A3rCeg8C2klCF4UN7iiYeUDVReQqU3MPvp8UjrxVaCXv94XHpKj4zKr4S+8ROfdr2sDAy80dtCi2cY9hpAmSNPMmu5Z5fcftoezy7+pRl5HsMvAzOgpP2QpDuYDPG/v4tiyjS5YeDEfyBCiChWG5RomkCm9etd6FWetkAmpOCVAGN5ttHk0kXwWZ/xDyaa/nCgRZJof2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=S+2WMphhalUbg3bUq5poKjZErBhzZcWd5MeZFGCRQfY=; b=bdhVVVgbIyZV93OlpJxpqXb8Nk4J3EcUglbVEE8aMsZhVoM6szoo+y+wqUY2IukYG4X97yZY4orZWLKkwxWKeRZVk/9dWrfkPs8fndyiw2CDCb0AkwP6hYWb88Y/E8XR7Ckg7te6HLqh/fQFM32tz+bTGukmfg8swuMqk25hDIoT4Tpwa4i3dp51lLtORtIeqA3kUW2BQMNZMZv9S5rzo6l8/JykuNWddr5pFeLo0jSMI7HH18bCwgEHKFpxv5pwG1hY1679XzL+fXEtezBSGFtWRGVXkv28QqX8Ft5DTEitapriUi3KVyyB1UrjXSrPSggesDDo36WKxDvvQDB88A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) by ZQ0PR01MB1112.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:c::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Fri, 3 May 2024 11:15:08 +0000 Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4]) by ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4%5]) with mapi id 15.20.7472.044; Fri, 3 May 2024 11:15:08 +0000 From: Alex Soo To: Linus Walleij , Bartosz Golaszewski , Hal Feng , Ley Foon Tan , Jianlong Huang , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alex Soo Subject: [RFC PATCH v3 7/7] riscv: dts: starfive: jh8100: add pinctrl device tree nodes Date: Fri, 3 May 2024 19:14:36 +0800 Message-Id: <20240503111436.113089-8-yuklin.soo@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240503111436.113089-1-yuklin.soo@starfivetech.com> References: <20240503111436.113089-1-yuklin.soo@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0011.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::20) To ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1176:EE_|ZQ0PR01MB1112:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c011065-33a8-4ac6-872a-08dc6b624aa4 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HYZBY7122z6e12k30ibXJZgqoaIYntNQTtyES0U1bEdu4+OspTEANQHuh1V1Z6tYVJK+v9NyLddVGqJvubIilWD5odVSc4LD8sY7SgGxBJBbcslasUzWTaxSzjcEg7LjI0tt6JnkwCXUZ7d2kIP8sYpyN8pIyN+Du5BJDJIRFI9ghInQ8Z9ONdVzlkxOSwW0+lK416A/jYaiR5ehLWTPtrM4arJrvUpJAW6OQg4oJrG5XchsLkRWuiUmcPEXpli+WjOFzQnAZ5OYy+82kTdUHt+f7JaH+nUTi5mspidgUdcmBPCqMCUknI3lWq2eOIXHo8ve10Xyzvh3puDnn+oj8hsl7f80TQFoLOH5TyGIAxd8KIgvud3W/uphy0ccBHYQrGIREIUxCzduGSn110rvxwzNUzwDp5aZ9imuZpkkwFcg5nvEgCdO8GpQr4yAUWUSNEDSp6shIgilYkgScEYIzERJZonZ8lIqNLaxfwhPpp0tDqFWGzJaDuRptRqRPwojkEKia0T44ZBUHxutGf8APpOxFCMGhoGM8ihNS8pi0KPcDA0nPrB52fP6aB53rbqqRl/e3QGnmO6YJtWexdweDVzXCj2CymCKaKI4KKl3HaNtbmMVv/zfWci70f5I5zn2sZ0S/xEHl+MStp/U91xurg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230031)(41320700004)(7416005)(1800799015)(52116005)(366007)(38350700005)(921011);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xR6qktZdJHshJTp64tRgVP+xgrF+x381IgrnSXpuZsvakBok5SWcsH3Pq6H2OUXkSS8X+n8GnrCQK1uzNleT4QzXpM2UG16szPFDZsgHewbPt3+zqthIs2FtJkvy7IjeN9SwtJNlqWQGZURohRn/rQ/Py2Hl8cdtqmb7eoFMzuCa/AcTa4iPoLUHzq70Yvz0bfn2haWKuoPXzis7Ra9dIdnBGNz4WQ4conJSRs5yPiholz17Spki2chlz1VyolCCSoe3AeM8ZC46JTFnjD5gv/YctId52JsyncjI+wla5486+Q4Tr3KDGipJakg1JhfAr7Tu+irK/gVIGDBjKT0RoGzTYU3v8x/Fv74fEcOXVzQbCmSnVoFPyYk8zA+K9pnonJDM4oppIa8e2vfIIKEqd6Fsk78PhBjSssc8U/UyOffVHNjBJFfW/gpmVVBPKWJ89qjpTptMFJJFZGDZEDUKyr2Jdq2kBUdAO9/BOhTdA4yCJ6QB7gkeSkCK5UetG5ar8MqCzr9Ih3yWuR+wtjq2qbWj0z6mwen4kIDj3wMa3NhkZDELz6cHdOvIPKISPV2yUMIgHrcwcZtkxxq9O/cAozMrnak3QUpPQ0yU/lAyDJena/d1f6+Xfqv9uH3TslCuhUwWkEkECzuEo6KMW81MH+HKq5T8obx97pzsbmaw6Qi9eLFbBnE8SnIitwhP4XFC2MKIW/INFPY+5V3lzCOLeixjMryPR8muUF/jEOxpT+IzN00Ql/1os8+V9X0b4SVuCpHvMiTJIvlFnQhw2JT4d9wA7ed+ptEY8NPNDtmsw+/O0BvkDsTcjMhvmBz81ueQExD4eKRVGhgfC8bHfCJ9WI33ynXLPTyZJDTVEal4IanVx1JvIZOVH+TwckKPH5Mg8wq/N6P4MiEdAovQxrVfcvGHN+yMM1I7imlsCiZ1Q7yBVZ/ixW1iDOvwM3UoKlKCQusjlzvqbYJo9icJ+ddL1xsDseJ8GbIUTFTm5grdWewoXMdiYxNQpsd/3lfnu2Ww/0tMr4JL6oYQNYsRbeKK6dipKoh8/QTJ3A+qXSpCnlJuL0jmRHJo3zuA5WKEUEvqbjXsbVqv/yVxNVGkGo9OteM4BI3W2dDVn+6aw7VkFPHEqvXKljHDGJ20PiKRZq1toNNNdVR1ZJpJq8/b7/eFJZKwGn4DwQgTCrKFHCflPwPwG9Smk1teJayNw5dAhr0cfmQDb0pYeduFtaDtTt78FVlQHTe69qDuKp/PDmpJkw48H0qHv0geWvVt+Ws2Epl0ttog8UjS2Y9stQws2rj9lY8eiZpAEGlpxCFU68Iuvf8GAwdqd/ydu7FNZbvVl1wKc8Onq0wdu1VXc/Rw6mxsbyARxlhpg6p325VUqVtaxY4/yMmJw04fg+UtSHPuLOSMLKYF1vlEzj6M6w9m9P3CkSWuDI/2+Hvueb+GvHf9OrxaYGhJF5v29E2/0JZYcN5Cvy8dYN3INHJzBQXtURN3lPvKkdDvTKlMBSWv8AVgJh16qT5oUdLn04YduolCtZ2eh0Om6OKnpPICdvYuD7ewwMxAWsucBNc+ixYI2z7UAQzUPtQ2fHSrF6PBPYbUp+dDmKAlVlGAScvHgKW1XBbTuQ== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5c011065-33a8-4ac6-872a-08dc6b624aa4 X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 11:15:08.4019 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: p2O9VFuQ1WWKjjjDP5L1tBeW+1ztcYchT5I10I0bUKS7ml2M7G2cd0Hxh+WSV70/KN9fbp1jNuBVAzjbLrGnVY4ZHizm1QT2snZc75RVnYE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1112 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240503_041514_165354_47611297 X-CRM114-Status: GOOD ( 13.65 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add pinctrl_east/pinctrl_west/pinctrl_gmac/pinctrl_aon device tree nodes for JH8100 SoC. Signed-off-by: Alex Soo --- arch/riscv/boot/dts/starfive/jh8100-evb.dts | 7 + arch/riscv/boot/dts/starfive/jh8100-pinfunc.h | 504 ++++++++++++++++++ arch/riscv/boot/dts/starfive/jh8100.dtsi | 46 ++ 3 files changed, 557 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh8100-pinfunc.h diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/dts/starfive/jh8100-evb.dts index c16bc25d8988..dde01ed35e3e 100644 --- a/arch/riscv/boot/dts/starfive/jh8100-evb.dts +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts @@ -4,6 +4,8 @@ */ #include "jh8100.dtsi" +#include "jh8100-pinfunc.h" +#include / { model = "StarFive JH8100 EVB"; @@ -26,3 +28,8 @@ memory@40000000 { &uart0 { status = "okay"; }; + +&pinctrl_aon { + wakeup-gpios = <&pinctrl_aon PAD_RGPIO1 GPIO_ACTIVE_HIGH>; + wakeup-source; +}; diff --git a/arch/riscv/boot/dts/starfive/jh8100-pinfunc.h b/arch/riscv/boot/dts/starfive/jh8100-pinfunc.h new file mode 100644 index 000000000000..0325338dee08 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh8100-pinfunc.h @@ -0,0 +1,504 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#ifndef __JH8100_PINFUNC_H__ +#define __JH8100_PINFUNC_H__ + +/* + * mux bits: + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din | dout | doen | function | gpio nr | + * + * dout: output signal + * doen: output enable signal + * din: optional input signal, 0xff = none + * function: + * gpio nr: gpio number, 0 - 63 + */ +#define GPIOMUX(n, dout, doen, din) ( \ + (((din) & 0xff) << 24) | \ + (((dout) & 0xff) << 16) | \ + (((doen) & 0x3f) << 10) | \ + ((n) & 0x3f)) + +#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff)) + +/* sys_iomux_east pins */ +#define PAD_GPIO0_E 0 +#define PAD_GPIO1_E 1 +#define PAD_GPIO2_E 2 +#define PAD_GPIO3_E 3 +#define PAD_GPIO4_E 4 +#define PAD_GPIO5_E 5 +#define PAD_GPIO6_E 6 +#define PAD_GPIO7_E 7 +#define PAD_GPIO8_E 8 +#define PAD_GPIO9_E 9 +#define PAD_GPIO10_E 10 +#define PAD_GPIO11_E 11 +#define PAD_GPIO12_E 12 +#define PAD_GPIO13_E 13 +#define PAD_GPIO14_E 14 +#define PAD_GPIO15_E 15 +#define PAD_GPIO16_E 16 +#define PAD_GPIO17_E 17 +#define PAD_GPIO18_E 18 +#define PAD_GPIO19_E 19 +#define PAD_GPIO20_E 20 +#define PAD_GPIO21_E 21 +#define PAD_GPIO22_E 22 +#define PAD_GPIO23_E 23 +#define PAD_GPIO24_E 24 +#define PAD_GPIO25_E 25 +#define PAD_GPIO26_E 26 +#define PAD_GPIO27_E 27 +#define PAD_GPIO28_E 28 +#define PAD_GPIO29_E 29 +#define PAD_GPIO30_E 30 +#define PAD_GPIO31_E 31 +#define PAD_GPIO32_E 32 +#define PAD_GPIO33_E 33 +#define PAD_GPIO34_E 34 +#define PAD_GPIO35_E 35 +#define PAD_GPIO36_E 36 +#define PAD_GPIO37_E 37 +#define PAD_GPIO38_E 38 +#define PAD_GPIO39_E 39 +#define PAD_GPIO40_E 40 +#define PAD_GPIO41_E 41 +#define PAD_GPIO42_E 42 +#define PAD_GPIO43_E 43 +#define PAD_GPIO44_E 44 +#define PAD_GPIO45_E 45 +#define PAD_GPIO46_E 46 +#define PAD_GPIO47_E 47 + +/* sys_iomux_west pins */ +#define PAD_GPIO0_W 0 +#define PAD_GPIO1_W 1 +#define PAD_GPIO2_W 2 +#define PAD_GPIO3_W 3 +#define PAD_GPIO4_W 4 +#define PAD_GPIO5_W 5 +#define PAD_GPIO6_W 6 +#define PAD_GPIO7_W 7 +#define PAD_GPIO8_W 8 +#define PAD_GPIO9_W 9 +#define PAD_GPIO10_W 10 +#define PAD_GPIO11_W 11 +#define PAD_GPIO12_W 12 +#define PAD_GPIO13_W 13 +#define PAD_GPIO14_W 14 +#define PAD_GPIO15_W 15 + +/* aon_iomux pins */ +#define PAD_RGPIO0 0 +#define PAD_RGPIO1 1 +#define PAD_RGPIO2 2 +#define PAD_RGPIO3 3 +#define PAD_RGPIO4 4 +#define PAD_RGPIO5 5 +#define PAD_RGPIO6 6 +#define PAD_RGPIO7 7 +#define PAD_RGPIO8 8 +#define PAD_RGPIO9 9 +#define PAD_RGPIO10 10 +#define PAD_RGPIO11 11 +#define PAD_RGPIO12 12 +#define PAD_RGPIO13 13 +#define PAD_RGPIO14 14 +#define PAD_RGPIO15 15 + +/* sys_iomux_east dout */ +#define GPOUT_LOW 0 +#define GPOUT_HIGH 1 +#define GPOUT_SYS_CAN0_STBY 2 +#define GPOUT_SYS_CAN0_TST_NEXT_BIT 3 +#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 4 +#define GPOUT_SYS_CAN0_TXD 5 +#define GPOUT_SYS_I2C0_CLK 6 +#define GPOUT_SYS_I2C0_DATA 7 +#define GPOUT_SYS_I2S0_STEREO_RSCKO 8 +#define GPOUT_SYS_I2S0_STEREO_RWSO 9 +#define GPOUT_SYS_I2S0_STEREO_SDO_0 10 +#define GPOUT_SYS_I2S0_STEREO_SDO_1 11 +#define GPOUT_SYS_I2S0_STEREO_TSCKO 12 +#define GPOUT_SYS_I2S0_STEREO_TWSO 13 +#define GPOUT_SYS_SPI0_MO 14 +#define GPOUT_SYS_SPI0_SS0 15 +#define GPOUT_SYS_SPI0_SS1 16 +#define GPOUT_SYS_SPI0_SS2 17 +#define GPOUT_SYS_SPI0_SS3 18 +#define GPOUT_SYS_SPI0_SCLK 19 +#define GPOUT_SYS_SPI0_SO 20 +#define GPOUT_SYS_UART0_DTR 21 +#define GPOUT_SYS_UART0_RTS 22 +#define GPOUT_SYS_UART0_TX 23 +#define GPOUT_SYS_USB0_DBG_DRIVE_VBUS 24 +#define GPOUT_SYS_PDM_MCLK 25 +#define GPOUT_SYS_PWM_CHANNEL0 26 +#define GPOUT_SYS_PWM_CHANNEL1 27 +#define GPOUT_SYS_PWM_CHANNEL2 28 +#define GPOUT_SYS_PWM_CHANNEL3 29 +#define GPOUT_SYS_PWM_CHANNEL4 30 +#define GPOUT_SYS_PWM_CHANNEL5 31 +#define GPOUT_SYS_PWM_CHANNEL6 32 +#define GPOUT_SYS_PWM_CHANNEL7 33 +#define GPOUT_SYS_SMBUS0_CLK 34 +#define GPOUT_SYS_SMBUS0_DATA 35 +#define GPOUT_SYS_SMBUS0_SUSPEND 36 +#define GPOUT_SYS_CLK_GCLK1 37 +#define GPOUT_SYS_CLK_GCLK2 38 +#define GPOUT_SYS_CLK_GCLK3 39 +#define GPOUT_SYS_CLK_GCLK4 40 +#define GPOUT_SYS_CLK_GCLK6 41 +#define GPOUT_SYS_CLK_GCLK7 42 +#define GPOUT_SYS_MCLK 43 +#define GPOUT_SYS_USB0_TYPEC_DRIVE_VBUS 44 +#define GPOUT_SYS_WATCHDOG0_RESET 45 +#define GPOUT_SYS_CAN1_STBY 46 +#define GPOUT_SYS_CAN1_TST_NEXT_BIT 47 +#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 48 +#define GPOUT_SYS_CAN1_TXD 49 +#define GPOUT_SYS_I2C1_CLK 50 +#define GPOUT_SYS_I2C1_DATA 51 +#define GPOUT_SYS_I2S1_RSCKO 52 +#define GPOUT_SYS_I2S1_RWSO 53 +#define GPOUT_SYS_I2S1_SDO0 54 +#define GPOUT_SYS_I2S1_SDO1 55 +#define GPOUT_SYS_I2S1_SDO2 56 +#define GPOUT_SYS_I2S1_SDO3 57 +#define GPOUT_SYS_I2S1_SDO4 58 +#define GPOUT_SYS_I2S1_SDO5 59 +#define GPOUT_SYS_I2S1_SDO6 60 +#define GPOUT_SYS_I2S1_SDO7 61 +#define GPOUT_SYS_I2S1_TSCKO 62 +#define GPOUT_SYS_I2S1_TWSO 63 +#define GPOUT_SYS_SDIO1_PU_PD_DATA2 64 +#define GPOUT_SYS_SDIO1_BUS_POWER 65 +#define GPOUT_SYS_SDIO1_RESET 66 +#define GPOUT_SYS_SDIO1_BUS_VOLTAGE_0 67 +#define GPOUT_SYS_SDIO1_BUS_VOLTAGE_1 68 +#define GPOUT_SYS_SDIO1_BUS_VOLTAGE_2 69 +#define GPOUT_SYS_SDIO1_LED 70 +#define GPOUT_SYS_SPI1_MO 71 +#define GPOUT_SYS_SPI1_SS0 72 +#define GPOUT_SYS_SPI1_SS1 73 +#define GPOUT_SYS_SPI1_SS2 74 +#define GPOUT_SYS_SPI1_SS3 75 +#define GPOUT_SYS_SPI1_SCLK 76 +#define GPOUT_SYS_SPI1_SO 77 +#define GPOUT_SYS_UART1_DTR 78 +#define GPOUT_SYS_UART1_RTS 79 +#define GPOUT_SYS_UART1_TX 80 +#define GPOUT_SYS_USB1_DBG_DRIVE_VBUS 81 +#define GPOUT_SYS_I2C2_CLK 82 +#define GPOUT_SYS_I2C2_DATA 83 +#define GPOUT_SYS_UART2_DTR 84 +#define GPOUT_SYS_UART2_RTS 85 +#define GPOUT_SYS_UART2_TX 86 +#define GPOUT_SYS_USB2_DBG_DRIVE_VBUS 87 +#define GPOUT_SYS_I2C3_CLK 88 +#define GPOUT_SYS_I2C3_DATA 89 +#define GPOUT_SYS_UART3_DTR 90 +#define GPOUT_SYS_UART3_RTS 91 +#define GPOUT_SYS_UART3_TX 92 +#define GPOUT_SYS_USB3_DBG_DRIVE_VBUS 93 +#define GPOUT_SYS_I2C4_CLK 94 +#define GPOUT_SYS_I2C4_DATA 95 +#define GPOUT_SYS_UART4_DTR 96 +#define GPOUT_SYS_UART4_RTS 97 +#define GPOUT_SYS_UART4_TX 98 +#define GPOUT_SYS_I2C5_CLK 99 +#define GPOUT_SYS_I2C5_DATA 100 + +/* sys_iomux_west dout */ +#define GPOUT_SYS_RSVD0 2 +#define GPOUT_SYS_RSVD1 3 +#define GPOUT_SYS_RSVD2 4 +#define GPOUT_SYS_RSVD3 5 +#define GPOUT_SYS_RSVD4 6 +#define GPOUT_SYS_RSVD5 7 +#define GPOUT_SYS_RSVD6 8 +#define GPOUT_SYS_RSVD7 9 +#define GPOUT_SYS_RSVD8 10 +#define GPOUT_SYS_HD_AUDIO0_BCLK 11 +#define GPOUT_SYS_HD_AUDIO0_RST 12 +#define GPOUT_SYS_HD_AUDIO0_SDI0_O 13 +#define GPOUT_SYS_HD_AUDIO0_SDI1_O 14 +#define GPOUT_SYS_HD_AUDIO0_SDO0 15 +#define GPOUT_SYS_HD_AUDIO0_SDO1 16 +#define GPOUT_SYS_HD_AUDIO0_SYNC 17 +#define GPOUT_SYS_HIFI4_JTAG_TDO 18 +#define GPOUT_SYS_CLK_GCLK5 19 +#define GPOUT_SYS_SMBUS1_CLK 20 +#define GPOUT_SYS_SMBUS1_DATA 21 +#define GPOUT_SYS_SMBUS1_SUSPEND 22 +#define GPOUT_SYS_SPI2_MO 23 +#define GPOUT_SYS_SPI2_SS0 24 +#define GPOUT_SYS_SPI2_SS1 25 +#define GPOUT_SYS_SPI2_SS2 26 +#define GPOUT_SYS_SPI2_SS3 27 +#define GPOUT_SYS_SPI2_SCLK 28 +#define GPOUT_SYS_SPI2_SO 29 +#define GPOUT_SYS_UART5_DTR 30 +#define GPOUT_SYS_UART5_RTS 31 +#define GPOUT_SYS_UART5_TX 32 +#define GPOUT_SYS_I2C6_CLK 33 +#define GPOUT_SYS_I2C6_DATA 34 +#define GPOUT_SYS_UART6_DTR 35 +#define GPOUT_SYS_UART6_RTS 36 +#define GPOUT_SYS_UART6_TX 37 +#define GPOUT_SYS_I2C7_CLK 38 +#define GPOUT_SYS_I2C7_DATA 39 + +/* aon_iomux dout */ +#define GPOUT_AON_CLK_32K 2 +#define GPOUT_AON_CLK_GCLK0 3 +#define GPOUT_AON_CLK_GCLK_OSC 4 +#define GPOUT_AON_SIG_STUB_POWER_EN_O 5 +#define GPOUT_AON_EMMC_PU_PD_DATA2 6 +#define GPOUT_AON_EMMC_BUS_POWER 7 +#define GPOUT_AON_EMMC_BUS_VOLTAGE_0 8 +#define GPOUT_AON_EMMC_BUS_VOLTAGE_1 9 +#define GPOUT_AON_EMMC_BUS_VOLTAGE_2 10 +#define GPOUT_AON_EMMC_LED 11 +#define GPOUT_AON_SDIO0_PU_PD_DATA2 12 +#define GPOUT_AON_SDIO0_BUS_POWER 13 +#define GPOUT_AON_SDIO0_RESET 14 +#define GPOUT_AON_SDIO0_BUS_VOLTAGE_0 15 +#define GPOUT_AON_SDIO0_BUS_VOLTAGE_1 16 +#define GPOUT_AON_SDIO0_BUS_VOLTAGE_2 17 +#define GPOUT_AON_SDIO0_LED 18 +#define GPOUT_AON_JTAG_TDO 19 +#define GPOUT_AON_SCP_POWER_EN 20 +#define GPOUT_AON_WATCHDOG1_RESET 21 +#define GPOUT_AON_UART7_TX 22 +#define GPOUT_AON_I2C8_CLK 23 +#define GPOUT_AON_I2C8_DATA 24 + +/* sys_iomux_east doen */ +#define GPOEN_SYS_ENABLE 0 +#define GPOEN_SYS_DISABLE 1 +#define GPOEN_SYS_I2C0_CLK 2 +#define GPOEN_SYS_I2C0_DATA 3 +#define GPOEN_SYS_I2S0_STEREO_SDOE_0 4 +#define GPOEN_SYS_I2S0_STEREO_SDOE_1 5 +#define GPOEN_SYS_SPI0_N_MO_EN 6 +#define GPOEN_SYS_SPI0_N_SCLK_EN 7 +#define GPOEN_SYS_SPI0_N_SO_EN 8 +#define GPOEN_SYS_SPI0_N_SS_EN 9 +#define GPOEN_SYS_PWM_CHANNEL0 10 +#define GPOEN_SYS_PWM_CHANNEL1 11 +#define GPOEN_SYS_PWM_CHANNEL2 12 +#define GPOEN_SYS_PWM_CHANNEL3 13 +#define GPOEN_SYS_PWM_CHANNEL4 14 +#define GPOEN_SYS_PWM_CHANNEL5 15 +#define GPOEN_SYS_PWM_CHANNEL6 16 +#define GPOEN_SYS_PWM_CHANNEL7 17 +#define GPOEN_SYS_SMBUS0_CLK 18 +#define GPOEN_SYS_SMBUS0_DATA 19 +#define GPOEN_SYS_SMBUS0_ALERT 20 +#define GPOEN_SYS_I2C1_CLK 21 +#define GPOEN_SYS_I2C1_DATA 22 +#define GPOEN_SYS_I2S1_SDO0 23 +#define GPOEN_SYS_I2S1_SDO1 24 +#define GPOEN_SYS_I2S1_SDO2 25 +#define GPOEN_SYS_I2S1_SDO3 26 +#define GPOEN_SYS_I2S1_SDO4 27 +#define GPOEN_SYS_I2S1_SDO5 28 +#define GPOEN_SYS_I2S1_SDO6 29 +#define GPOEN_SYS_I2S1_SDO7 30 +#define GPOEN_SYS_SPI1_N_MO_EN 31 +#define GPOEN_SYS_SPI1_N_SCLK_EN 32 +#define GPOEN_SYS_SPI1_N_SO_EN 33 +#define GPOEN_SYS_SPI1_N_SS_EN 34 +#define GPOEN_SYS_I2C2_CLK 35 +#define GPOEN_SYS_I2C2_DATA 36 +#define GPOEN_SYS_I2C3_CLK 37 +#define GPOEN_SYS_I2C3_DATA 38 +#define GPOEN_SYS_I2C4_CLK 39 +#define GPOEN_SYS_I2C4_DATA 40 +#define GPOEN_SYS_I2C5_CLK 41 +#define GPOEN_SYS_I2C5_DATA 42 + +/* sys_iomux_west doen */ +#define GPOEN_SYS_RSVD0 2 +#define GPOEN_SYS_RSVD1 3 +#define GPOEN_SYS_RSVD2 4 +#define GPOEN_SYS_RSVD3 5 +#define GPOEN_SYS_RSVD4 6 +#define GPOEN_SYS_RSVD5 7 +#define GPOEN_SYS_RSVD6 8 +#define GPOEN_SYS_HD_AUDIO0_SDI0 9 +#define GPOEN_SYS_HD_AUDIO0_SDI1 10 +#define GPOEN_SYS_HIFI4_JTAG_TDO 11 +#define GPOEN_SYS_SMBUS1_CLK 12 +#define GPOEN_SYS_SMBUS1_DATA 13 +#define GPOEN_SYS_SMBUS1_ALERT 14 +#define GPOEN_SYS_SPI2_MO 15 +#define GPOEN_SYS_SPI2_SCLK 16 +#define GPOEN_SYS_SPI2_SO 17 +#define GPOEN_SYS_SPI2_SS 18 +#define GPOEN_SYS_I2C6_CLK 19 +#define GPOEN_SYS_I2C6_DATA 20 +#define GPOEN_SYS_I2C7_CLK 21 +#define GPOEN_SYS_I2C7_DATA 22 + +/* aon_iomux doen */ +#define GPOEN_AON_JTAG_TDO 2 +#define GPOEN_AON_I2C8_CLK 3 +#define GPOEN_AON_I2C8_DATA 4 + +/* sys_iomux din */ +#define GPI_NONE 255 + +/* sys_iomux_east din */ +#define GPI_SYS_CAN0_RXD 0 +#define GPI_SYS_I2C0_CLK 1 +#define GPI_SYS_I2C0_DATA 2 +#define GPI_SYS_SPI0_SCLK 3 +#define GPI_SYS_SPI0_MI 4 +#define GPI_SYS_SPI0_SS_N 5 +#define GPI_SYS_SPI0_SI 6 +#define GPI_SYS_UART0_CTS 7 +#define GPI_SYS_UART0_DCD 8 +#define GPI_SYS_UART0_DSR 9 +#define GPI_SYS_UART0_RI 10 +#define GPI_SYS_UART0_RX 11 +#define GPI_SYS_USB0_DBG_OVERCURRENT 12 +#define GPI_SYS_PDM_DMIC0 13 +#define GPI_SYS_PDM_DMIC1 14 +#define GPI_SYS_I2SRX0_SDIN0 15 +#define GPI_SYS_I2SRX0_SDIN1 16 +#define GPI_SYS_SMBUS0_CLK 17 +#define GPI_SYS_SMBUS0_DATA 18 +#define GPI_SYS_SMBUS0_ALERT 19 +#define GPI_SYS_JTAG_TCK 20 +#define GPI_SYS_MCLK_EXT 21 +#define GPI_SYS_I2SRX0_BCLK 22 +#define GPI_SYS_I2SRX0_LRCK 23 +#define GPI_SYS_I2STX0_BCLK 24 +#define GPI_SYS_I2STX0_LRCK 25 +#define GPI_SYS_SPI0_SCLK_IN0 26 +#define GPI_SYS_SPI0_SCLK_IN1 27 +#define GPI_SYS_I2S0_STEREO_RX_BCLK 28 +#define GPI_SYS_I2S0_STEREO_RX_LRCK 29 +#define GPI_SYS_I2S0_STEREO_TX_BCLK 30 +#define GPI_SYS_I2S0_STEREO_TX_LRCK 31 +#define GPI_SYS_I2S1_RX_BCLK 32 +#define GPI_SYS_I2S1_RX_LRCK 33 +#define GPI_SYS_I2S1_TX_BCLK 34 +#define GPI_SYS_I2S1_TX_LRCK 35 +#define GPI_SYS_USB0_TYPEC_OVERCURRENT 36 +#define GPI_SYS_CAN1_RXD 37 +#define GPI_SYS_I2C1_CLK 38 +#define GPI_SYS_I2C1_DATA 39 +#define GPI_SYS_I2S1_SDI_0 40 +#define GPI_SYS_I2S1_SDI_1 41 +#define GPI_SYS_I2S1_SDI_2 42 +#define GPI_SYS_I2S1_SDI_3 43 +#define GPI_SYS_I2S1_SDI_4 44 +#define GPI_SYS_I2S1_SDI_5 45 +#define GPI_SYS_I2S1_SDI_6 46 +#define GPI_SYS_I2S1_SDI_7 47 +#define GPI_SYS_SDIO1_CARD_DETECT 48 +#define GPI_SYS_SDIO1_WRITE_PROTECT 49 +#define GPI_SYS_SPI1_EXT_CLK 50 +#define GPI_SYS_SPI1_MI 51 +#define GPI_SYS_SPI1_SS_IN 52 +#define GPI_SYS_SPI1_SI 53 +#define GPI_SYS_UART1_CTS 54 +#define GPI_SYS_UART1_DCD 55 +#define GPI_SYS_UART1_DSR 56 +#define GPI_SYS_UART1_RI 57 +#define GPI_SYS_UART1_RX 58 +#define GPI_SYS_USB1_DBG_OVERCURRENT 59 +#define GPI_SYS_I2C2_CLK 60 +#define GPI_SYS_I2C2_DATA 61 +#define GPI_SYS_UART2_CTS 62 +#define GPI_SYS_UART2_DCD 63 +#define GPI_SYS_UART2_DSR 64 +#define GPI_SYS_UART2_RI 65 +#define GPI_SYS_UART2_RX 66 +#define GPI_SYS_USB2_DBG_OVERCURRENT 67 +#define GPI_SYS_I2C3_CLK 68 +#define GPI_SYS_I2C3_DATA 69 +#define GPI_SYS_UART3_CTS 70 +#define GPI_SYS_UART3_DCD 71 +#define GPI_SYS_UART3_DSR 72 +#define GPI_SYS_UART3_RI 73 +#define GPI_SYS_UART3_RX 74 +#define GPI_SYS_USB3_DBG_OVERCURRENT 75 +#define GPI_SYS_I2C4_CLK 76 +#define GPI_SYS_I2C4_DATA 77 +#define GPI_SYS_UART4_CTS 78 +#define GPI_SYS_UART4_DCD 79 +#define GPI_SYS_UART4_DSR 80 +#define GPI_SYS_UART4_RI 81 +#define GPI_SYS_UART4_RX 82 +#define GPI_SYS_I2C5_CLK 83 +#define GPI_SYS_I2C5_DATA 84 + +/* sys_iomux_west din */ +#define GPI_SYS_RSVD0 0 +#define GPI_SYS_RSVD1 1 +#define GPI_SYS_RSVD2 2 +#define GPI_SYS_RSVD3 3 +#define GPI_SYS_RSVD4 4 +#define GPI_SYS_RSVD5 5 +#define GPI_SYS_RSVD6 6 +#define GPI_SYS_HD_AUDIO0_SDI0_I 7 +#define GPI_SYS_HD_AUDIO0_SDI1_I 8 +#define GPI_SYS_HIFI4_JTAG_TDI 9 +#define GPI_SYS_HIFI4_JTAG_TMS 10 +#define GPI_SYS_HIFI4_JTAG_RST 11 +#define GPI_SYS_RSVD7 12 +#define GPI_SYS_HIFI4_JTAG_TCK 13 +#define GPI_SYS_RSVD8 14 +#define GPI_SYS_SPI0_SCLK_IN2 15 +#define GPI_SYS_SMBUS1_CLK 16 +#define GPI_SYS_SMBUS1_DATA 17 +#define GPI_SYS_SMBUS1_ALERT 18 +#define GPI_SYS_SPI2_EXT_CLK 19 +#define GPI_SYS_SPI2_MI 20 +#define GPI_SYS_SPI2_SS_IN 21 +#define GPI_SYS_SPI2_SI 22 +#define GPI_SYS_UART5_CTS 23 +#define GPI_SYS_UART5_DCD 24 +#define GPI_SYS_UART5_DSR 25 +#define GPI_SYS_UART5_RI 26 +#define GPI_SYS_UART5_RX 27 +#define GPI_SYS_I2C6_CLK 28 +#define GPI_SYS_I2C6_DATA 29 +#define GPI_SYS_UART6_CTS 30 +#define GPI_SYS_UART6_DCD 31 +#define GPI_SYS_UART6_DSR 32 +#define GPI_SYS_UART6_RI 33 +#define GPI_SYS_UART6_RX 34 +#define GPI_SYS_I2C7_CLK 35 +#define GPI_SYS_I2C7_DATA 36 + +/* aon_iomux din */ +#define GPI_AON_JTAG_TCK 0 +#define GPI_AON_SIG_STUB_RESERVED_0 1 +#define GPI_AON_SIG_STUB_RESERVED_1 2 +#define GPI_AON_SIG_STUB_RESERVED_2 3 +#define GPI_AON_XSPI0_GP_OPEN_DRAIN_0 4 +#define GPI_AON_XSPI0_GP_OPEN_DRAIN_1 5 +#define GPI_AON_XSPI0_GP_OPEN_DRAIN_2 6 +#define GPI_AON_XSPI0_GP_OPEN_DRAIN_3 7 +#define GPI_AON_SDIO0_CARD_DETECTION 8 +#define GPI_AON_SDIO0_WRITE_PROTECTION 9 +#define GPI_AON_SRC_BUF_JTAG_RST 10 +#define GPI_AON_JTAG_TDI 11 +#define GPI_AON_JTAG_TMS 12 +#define GPI_AON_UART7_RX 13 +#define GPI_AON_I2C8_CLK 14 +#define GPI_AON_I2C8_DATA 15 + +#endif diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi index 5ba826e38ead..37251010d96f 100644 --- a/arch/riscv/boot/dts/starfive/jh8100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include +#include #include / { @@ -563,6 +564,19 @@ uart4: serial@121a0000 { status = "disabled"; }; + pinctrl_east: pinctrl@122d0000 { + compatible = "starfive,jh8100-sys-pinctrl-east", + "syscon", "simple-mfd"; + reg = <0x0 0x122d0000 0x0 0x10000>; + clocks = <&necrg JH8100_NECLK_IOMUX_EAST_PCLK>; + resets = <&necrg JH8100_NERST_SYS_IOMUX_E>; + interrupts = <182>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_east 0 0 48>; + }; + necrg: clock-controller@12320000 { compatible = "starfive,jh8100-necrg"; reg = <0x0 0x12320000 0x0 0x10000>; @@ -634,6 +648,19 @@ nwcrg: clock-controller@123c0000 { #reset-cells = <1>; }; + pinctrl_west: pinctrl@123e0000 { + compatible = "starfive,jh8100-sys-pinctrl-west", + "syscon", "simple-mfd"; + reg = <0x0 0x123e0000 0x0 0x10000>; + clocks = <&nwcrg JH8100_NWCLK_IOMUX_WEST_PCLK>; + resets = <&nwcrg JH8100_NWRST_SYS_IOMUX_W>; + interrupts = <183>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_west 0 0 16>; + }; + syscrg: clock-controller@126d0000 { compatible = "starfive,jh8100-syscrg"; reg = <0x0 0x126d0000 0x0 0x10000>; @@ -656,6 +683,13 @@ swcrg: clock-controller@12720000 { #reset-cells = <1>; }; + pinctrl_gmac: pinctrl@12770000 { + compatible = "starfive,jh8100-sys-pinctrl-gmac", + "syscon", "simple-mfd"; + status = "disabled"; + reg = <0x0 0x12770000 0x0 0x10000>; + }; + uart5: serial@127d0000 { compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; reg = <0x0 0x127d0000 0x0 0x10000>; @@ -674,6 +708,18 @@ uart6: serial@127e0000 { status = "disabled"; }; + pinctrl_aon: pinctrl@1f300000 { + compatible = "starfive,jh8100-aon-pinctrl", + "syscon", "simple-mfd"; + reg = <0x0 0x1f300000 0x0 0x10000>; + resets = <&aoncrg JH8100_AONRST_AON_IOMUX_PRESETN>; + interrupts = <160>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aon 0 0 16>; + }; + aoncrg: clock-controller@1f310000 { compatible = "starfive,jh8100-aoncrg"; reg = <0x0 0x1f310000 0x0 0x10000>;