[v2] ARM: tegra: add Acer Chromebook 13 device tree

Commit Message

Dylan Reid Aug. 13, 2014, 7:14 p.m. UTC

The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
processor and is similar to the Venice2 reference platform.

The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
and work on the 1266x768 models.  The HD models haven't yet been
tested.

WiFi does not work yet, it needs at least some PMIC changes to enable
the 32k clock.

The elan trackpad is not yet functional but hopefully will be soon as
there are patches under review.

There is also an issue on reboot because the TPM isn't reset.  It will
cause the stock firmware to enter recovery mode.  This can be worked
around by an EC-reset, press the refresh and power keys at the same
time.

Signed-off-by: Dylan Reid <[e-mail]>
---
 arch/arm/boot/dts/Makefile              |    1 +
 arch/arm/boot/dts/tegra124-nyan-big.dts | 1136 +++++++++++++++++++++++++++++++
 2 files changed, 1137 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra124-nyan-big.dts

Comments

Andreas Färber Aug. 16, 2014, 3:20 p.m. UTC | #1

Hi,

Am 13.08.2014 21:14, schrieb Dylan Reid:
> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
> processor and is similar to the Venice2 reference platform.
> 
> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
> and work on the 1266x768 models.  The HD models haven't yet been

1366?

> tested.
> 
> WiFi does not work yet, it needs at least some PMIC changes to enable
> the 32k clock.
> 
> The elan trackpad is not yet functional but hopefully will be soon as
> there are patches under review.
> 
> There is also an issue on reboot because the TPM isn't reset.  It will
> cause the stock firmware to enter recovery mode.  This can be worked
> around by an EC-reset, press the refresh and power keys at the same
> time.
> 
> Signed-off-by: Dylan Reid <[e-mail]>
> ---
>  arch/arm/boot/dts/Makefile              |    1 +
>  arch/arm/boot/dts/tegra124-nyan-big.dts | 1136 +++++++++++++++++++++++++++++++
>  2 files changed, 1137 insertions(+)
>  create mode 100644 arch/arm/boot/dts/tegra124-nyan-big.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index acb6b42..bebb4e7 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -439,6 +439,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
>  	tegra114-dalmore.dtb \
>  	tegra114-roth.dtb \
>  	tegra114-tn7.dtb \
> +	tegra124-nyan-big.dtb \
>  	tegra124-jetson-tk1.dtb \

"nyan" goes here alphabetically (still ordered as "big").

>  	tegra124-venice2.dtb
>  dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
> diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
> new file mode 100644
> index 0000000..79f1852
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
> @@ -0,0 +1,1136 @@
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include "tegra124.dtsi"
> +
> +/ {
> +	model = "Acer Chromebook 13";
> +	compatible = "google,nyan-big", "nvidia,tegra124";

In light of v1 and the above commit message referring to this as Google
Big, shouldn't this be "google,big", "nvidia,tegra124" and optionally
"google,nyan" as secondary string, independent of the new file name?

The Exynos5250 based Chromebooks use "google,snow" and "google,spring"
respectively, and I don't think there's any mention of Daisy at all in
upstream, unlike some ChromeOS sources.

Also, should we start documenting these google,* compatible strings to
please checkpatch.pl?

> +
> +	aliases {
> +		rtc0 = "/i2c@0,7000d000/pmic@40";
> +		rtc1 = "/rtc@0,7000e000";
> +	};
> +
> +	memory {
> +		reg = <0x0 0x80000000 0x0 0x80000000>;
> +	};
> +
> +	host1x@0,50000000 {
> +		hdmi@0,54280000 {
> +			status = "okay";
> +
> +			vdd-supply = <&vdd_3v3_hdmi>;
> +			pll-supply = <&vdd_hdmi_pll>;
> +			hdmi-supply = <&vdd_5v0_hdmi>;
> +
> +			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> +			nvidia,hpd-gpio =
> +				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		sor@0,54540000 {
> +			status = "okay";
> +
> +			nvidia,dpaux = <&dpaux>;
> +			nvidia,panel = <&panel>;
> +		};
> +
> +		dpaux: dpaux@0,545c0000 {
> +			vdd-supply = <&vdd_3v3_panel>;
> +			status = "okay";
> +		};
> +	};
> +
> +	pinmux: pinmux@0,70000868 {
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinmux_default>;
> +
> +		pinmux_default: common {
> +			dap_mclk1_pw4 {

Any need to have the nodes this way? Shouldn't this rather be
dap-mclk1-pw4 as node name by conventions, with a dap_mclk1_pw4 label
for referencing if needed? Same below, obviously.

> +				nvidia,pins = "dap_mclk1_pw4";
> +				nvidia,function = "extperiph1";
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			dap2_din_pa4 {
> +				nvidia,pins = "dap2_din_pa4";
> +				nvidia,function = "i2s1";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			dap2_dout_pa5 {
> +				nvidia,pins = "dap2_dout_pa5",
> +					      "dap2_fs_pa2",
> +					      "dap2_sclk_pa3";
> +				nvidia,function = "i2s1";
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			dvfs_pwm_px0 {
> +				nvidia,pins = "dvfs_pwm_px0",
> +					      "dvfs_clk_px2";
> +				nvidia,function = "cldvfs";
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			ulpi_clk_py0 {
> +				nvidia,pins = "ulpi_clk_py0",
> +					      "ulpi_nxt_py2",
> +					      "ulpi_stp_py3";
> +				nvidia,function = "spi1";
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			ulpi_dir_py1 {
> +				nvidia,pins = "ulpi_dir_py1";
> +				nvidia,function = "spi1";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			cam_i2c_scl_pbb1 {
> +				nvidia,pins = "cam_i2c_scl_pbb1",
> +					      "cam_i2c_sda_pbb2";
> +				nvidia,function = "i2c3";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,lock = <TEGRA_PIN_DISABLE>;
> +				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> +			};
> +			gen2_i2c_scl_pt5 {
> +				nvidia,pins = "gen2_i2c_scl_pt5",
> +					      "gen2_i2c_sda_pt6";
> +				nvidia,function = "i2c2";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,lock = <TEGRA_PIN_DISABLE>;
> +				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> +			};
> +			pg4 {
> +				nvidia,pins = "pg4",
> +					      "pg5",
> +					      "pg6",
> +					      "pi3";
> +				nvidia,function = "spi4";
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			pg7 {
> +				nvidia,pins = "pg7";
> +				nvidia,function = "spi4";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			ph1 {
> +				nvidia,pins = "ph1";
> +				nvidia,function = "pwm1";
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			pk0 {
> +				nvidia,pins = "pk0",
> +					      "kb_row15_ps7",
> +					      "clk_32k_out_pa0";
> +				nvidia,function = "soc";
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +			sdmmc1_clk_pz0 {
> +				nvidia,pins = "sdmmc1_clk_pz0";
> +				nvidia,function = "sdmmc1";
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			sdmmc1_cmd_pz1 {
> +				nvidia,pins = "sdmmc1_cmd_pz1",
> +					      "sdmmc1_dat0_py7",
> +					      "sdmmc1_dat1_py6",
> +					      "sdmmc1_dat2_py5",
> +					      "sdmmc1_dat3_py4";
> +				nvidia,function = "sdmmc1";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			sdmmc3_clk_pa6 {
> +				nvidia,pins = "sdmmc3_clk_pa6";
> +				nvidia,function = "sdmmc3";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			sdmmc3_cmd_pa7 {
> +				nvidia,pins = "sdmmc3_cmd_pa7",
> +					      "sdmmc3_dat0_pb7",
> +					      "sdmmc3_dat1_pb6",
> +					      "sdmmc3_dat2_pb5",
> +					      "sdmmc3_dat3_pb4",
> +					      "kb_col4_pq4",
> +					      "sdmmc3_clk_lb_out_pee4",
> +					      "sdmmc3_clk_lb_in_pee5",
> +					      "sdmmc3_cd_n_pv2";
> +				nvidia,function = "sdmmc3";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			sdmmc4_clk_pcc4 {
> +				nvidia,pins = "sdmmc4_clk_pcc4";
> +				nvidia,function = "sdmmc4";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			sdmmc4_cmd_pt7 {
> +				nvidia,pins = "sdmmc4_cmd_pt7",
> +					      "sdmmc4_dat0_paa0",
> +					      "sdmmc4_dat1_paa1",
> +					      "sdmmc4_dat2_paa2",
> +					      "sdmmc4_dat3_paa3",
> +					      "sdmmc4_dat4_paa4",
> +					      "sdmmc4_dat5_paa5",
> +					      "sdmmc4_dat6_paa6",
> +					      "sdmmc4_dat7_paa7";
> +				nvidia,function = "sdmmc4";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			pwr_i2c_scl_pz6 {
> +				nvidia,pins = "pwr_i2c_scl_pz6",
> +					      "pwr_i2c_sda_pz7";
> +				nvidia,function = "i2cpwr";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,lock = <TEGRA_PIN_DISABLE>;
> +				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> +			};
> +			jtag_rtck {
> +				nvidia,pins = "jtag_rtck";
> +				nvidia,function = "rtck";
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			clk_32k_in {
> +				nvidia,pins = "clk_32k_in";
> +				nvidia,function = "clk";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			core_pwr_req {
> +				nvidia,pins = "core_pwr_req";
> +				nvidia,function = "pwron";
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			cpu_pwr_req {
> +				nvidia,pins = "cpu_pwr_req";
> +				nvidia,function = "cpu";
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			pwr_int_n {
> +				nvidia,pins = "pwr_int_n";
> +				nvidia,function = "pmi";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			reset_out_n {
> +				nvidia,pins = "reset_out_n";
> +				nvidia,function = "reset_out_n";
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			clk3_out_pee0 {
> +				nvidia,pins = "clk3_out_pee0";
> +				nvidia,function = "extperiph3";
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			gen1_i2c_sda_pc5 {
> +				nvidia,pins = "gen1_i2c_sda_pc5",
> +					      "gen1_i2c_scl_pc4";
> +				nvidia,function = "i2c1";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,lock = <TEGRA_PIN_DISABLE>;
> +				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> +			};
> +			hdmi_cec_pee3 {
> +				nvidia,pins = "hdmi_cec_pee3";
> +				nvidia,function = "cec";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,lock = <TEGRA_PIN_DISABLE>;
> +				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
> +			};
> +			hdmi_int_pn7 {
> +				nvidia,pins = "hdmi_int_pn7";
> +				nvidia,function = "rsvd1";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			};
> +			ddc_scl_pv4 {
> +				nvidia,pins = "ddc_scl_pv4",
> +					      "ddc_sda_pv5";
> +				nvidia,function = "i2c4";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,lock = <TEGRA_PIN_DISABLE>;
> +				nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
> +			};
> +			kb_row10_ps2 {
> +				nvidia,pins = "kb_row10_ps2";
> +				nvidia,function = "uarta";
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +			kb_row9_ps1 {
> +				nvidia,pins = "kb_row9_ps1";
> +				nvidia,function = "uarta";
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +			};
> +			usb_vbus_en0_pn4 {
> +				nvidia,pins = "usb_vbus_en0_pn4",
> +					      "usb_vbus_en1_pn5";
> +				nvidia,function = "usb";
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,lock = <TEGRA_PIN_DISABLE>;
> +				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> +			};
> +			drive_sdio1 {
> +				nvidia,pins = "drive_sdio1";
> +				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
> +				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull-down-strength = <36>;
> +				nvidia,pull-up-strength = <20>;
> +				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
> +				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
> +			};
> +			drive_sdio3 {
> +				nvidia,pins = "drive_sdio3";
> +				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
> +				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull-down-strength = <22>;
> +				nvidia,pull-up-strength = <36>;
> +				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
> +				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
> +			};
> +			drive_gma {
> +				nvidia,pins = "drive_gma";
> +				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
> +				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
> +				nvidia,pull-down-strength = <2>;
> +				nvidia,pull-up-strength = <1>;
> +				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
> +				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
> +				nvidia,drive-type = <1>;
> +			};
> +			codec_irq_l {
> +				nvidia,pins = "ph4";
> +				nvidia,function = "gmi";
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +			lcd_bl_en {
> +				nvidia,pins = "ph2";
> +				nvidia,function = "gmi";
> +				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +			};
> +			touch_irq_l {
> +				nvidia,pins = "gpio_w3_aud_pw3";
> +				nvidia,function = "spi6";
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +			tpm_davint_l {
> +				nvidia,pins = "ph6";
> +				nvidia,function = "gmi";
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +			ts_irq_l {
> +				nvidia,pins = "pk2";
> +				nvidia,function = "gmi";
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +			ts_reset_l {
> +				nvidia,pins = "pk4";
> +				nvidia,function = "gmi";
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +			};
> +			ts_shdn_l {
> +				nvidia,pins = "pk1";
> +				nvidia,function = "gmi";
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +			};
> +			ph7 {
> +				nvidia,pins = "ph7";
> +				nvidia,function = "gmi";
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +			kb_col0_ap {
> +				nvidia,pins = "kb_col0_pq0";
> +				nvidia,function = "rsvd4";
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +			lid_open {
> +				nvidia,pins = "kb_row4_pr4";
> +				nvidia,function = "rsvd3";
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +			en_vdd_sd {
> +				nvidia,pins = "kb_row0_pr0";
> +				nvidia,function = "rsvd4";
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +			};
> +			ac_ok {
> +				nvidia,pins = "pj0";
> +				nvidia,function = "gmi";
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +			sensor_irq_l {
> +				nvidia,pins = "pi6";
> +				nvidia,function = "gmi";
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +			wifi_en {
> +				nvidia,pins = "gpio_x7_aud_px7";
> +				nvidia,function = "rsvd4";
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +			};
> +			en_vdd_bl {
> +				nvidia,pins = "dap3_dout_pp2";
> +				nvidia,function = "i2s2";
> +				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +			};
> +			en_vdd_hdmi {
> +				nvidia,pins = "spdif_in_pk6";
> +				nvidia,function = "spdif";
> +				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +			};
> +			soc_warm_reset_l {
> +				nvidia,pins = "pi5";
> +				nvidia,function = "gmi";
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +			};
> +			hp_det_l {
> +				nvidia,pins = "pi7";
> +				nvidia,function = "rsvd1";
> +				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +			mic_det_l {
> +				nvidia,pins = "kb_row7_pr7";
> +				nvidia,function = "rsvd2";
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +		};
> +	};
> +
> +	serial@0,70006000 {
> +		/* Debug connector on the bottom of the board near SD card. */
> +		status = "okay";
> +	};
> +
> +	pwm: pwm@0,7000a000 {

Add the label to the .dtsi where the node is first declared? Then you
can override it the safer &pwm { ... }; way. Same for all other nodes
being extended/overridden here - that's what your colleagues requested
for Spring. It'll help with the 80 char limit further below by reducing
indentation.

> +		status = "okay";
> +	};
> +
> +	i2c@0,7000c000 {
> +		status = "okay";
> +		clock-frequency = <100000>;
> +
> +		acodec: audio-codec@10 {
> +			compatible = "maxim,max98090";
> +			reg = <0x10>;
> +			interrupt-parent = <&gpio>;
> +			interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		temperature-sensor@4c {
> +			compatible = "ti,tmp451";
> +			reg = <0x4c>;
> +			interrupt-parent = <&gpio>;
> +			interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
> +
> +			#thermal-sensor-cells = <1>;
> +		};
> +	};
> +
> +	i2c@0,7000c400 {
> +		status = "okay";
> +		clock-frequency = <100000>;
> +	};
> +
> +	i2c@0,7000c500 {
> +		status = "okay";
> +		clock-frequency = <400000>;
> +
> +		tpm@20 {
> +			compatible = "infineon,slb9645tt";
> +			reg = <0x20>;
> +		};
> +	};
> +
> +	hdmi_ddc: i2c@0,7000c700 {
> +		status = "okay";
> +		clock-frequency = <100000>;
> +	};
> +
> +	i2c@0,7000d000 {
> +		status = "okay";
> +		clock-frequency = <400000>;
> +
> +		pmic: pmic@40 {
> +			compatible = "ams,as3722";
> +			reg = <0x40>;
> +			interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			ams,system-power-controller;
> +
> +			#interrupt-cells = <2>;
> +			interrupt-controller;
> +
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&as3722_default>;
> +
> +			as3722_default: pinmux {
> +				gpio0 {
> +					pins = "gpio0";
> +					function = "gpio";
> +					bias-pull-down;
> +				};
> +
> +				gpio1 {
> +					pins = "gpio1";
> +					function = "gpio";
> +					bias-pull-up;
> +				};
> +
> +				gpio2_4_7 {
> +					pins = "gpio2", "gpio4", "gpio7";
> +					function = "gpio";
> +					bias-pull-up;
> +				};
> +
> +				gpio3_6 {
> +					pins = "gpio3", "gpio6";
> +					bias-high-impedance;
> +				};
> +
> +				gpio5 {
> +					pins = "gpio5";
> +					function = "clk32k-out";
> +					bias-pull-down;
> +				};
> +			};
> +
> +			regulators {
> +				vsup-sd2-supply = <&vdd_5v0_sys>;
> +				vsup-sd3-supply = <&vdd_5v0_sys>;
> +				vsup-sd4-supply = <&vdd_5v0_sys>;
> +				vsup-sd5-supply = <&vdd_5v0_sys>;
> +				vin-ldo0-supply = <&vdd_1v35_lp0>;
> +				vin-ldo1-6-suasked mepply = <&vdd_3v3_run>;
> +				vin-ldo2-5-7-supply = <&vddio_1v8>;
> +				vin-ldo3-4-supply = <&vdd_3v3_sys>;
> +				vin-ldo9-10-supply = <&vdd_5v0_sys>;
> +				vin-ldo11-supply = <&vdd_3v3_run>;
> +
> +				sd0 {
> +					regulator-name = "+VDD_CPU_AP";
> +					regulator-min-microvolt = <700000>;
> +					regulator-max-microvolt = <1350000>;
> +					regulator-min-microamp = <3500000>;
> +					regulator-max-microamp = <3500000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +					ams,ext-control = <2>;
> +				};
> +
> +				sd1 {
> +					regulator-name = "+VDD_CORE";
> +					regulator-min-microvolt = <700000>;
> +					regulator-max-microvolt = <1350000>;
> +					regulator-min-microamp = <2500000>;
> +					regulator-max-microamp = <4000000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +					ams,ext-control = <1>;
> +				};
> +
> +				vdd_1v35_lp0: sd2 {
> +					regulator-name = "+1.35V_LP0(sd2)";
> +					regulator-min-microvolt = <1350000>;
> +					regulator-max-microvolt = <1350000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +				};
> +
> +				sd3 {
> +					regulator-name = "+1.35V_LP0(sd3)";
> +					regulator-min-microvolt = <1350000>;
> +					regulator-max-microvolt = <1350000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +				};
> +
> +				vdd_1v05_run: sd4 {
> +					regulator-name = "+1.05V_RUN";
> +					regulator-min-microvolt = <1050000>;
> +					regulator-max-microvolt = <1050000>;
> +				};
> +
> +				vddio_1v8: sd5 {
> +					regulator-name = "+1.8V_VDDIO";
> +					regulator-min-microvolt = <1800000>;
> +					regulator-max-microvolt = <1800000>;
> +					regulator-boot-on;
> +					regulator-always-on;
> +				};
> +
> +				sd6 {
> +					regulator-name = "+VDD_GPU_AP";
> +					regulator-min-microvolt = <650000>;
> +					regulator-max-microvolt = <1200000>;
> +					regulator-min-microamp = <3500000>;
> +					regulator-max-microamp = <3500000>;
> +					regulator-boot-on;
> +					regulator-always-on;
> +				};
> +
> +				ldo0 {
> +					regulator-name = "+1.05V_RUN_AVDD";
> +					regulator-min-microvolt = <1050000>;
> +					regulator-max-microvolt = <1050000>;
> +					regulator-boot-on;
> +					regulator-always-on;
> +					ams,ext-control = <1>;
> +				};
> +
> +				ldo1 {
> +					regulator-name = "+1.8V_RUN_CAM";
> +					regulator-min-microvolt = <1800000>;
> +					regulator-max-microvolt = <1800000>;
> +				};
> +
> +				ldo2 {
> +					regulator-name = "+1.2V_GEN_AVDD";
> +					regulator-min-microvolt = <1200000>;
> +					regulator-max-microvolt = <1200000>;
> +					regulator-boot-on;
> +					regulator-always-on;
> +				};
> +
> +				ldo3 {
> +					regulator-name = "+1.00V_LP0_VDD_RTC";
> +					regulator-min-microvolt = <1000000>;
> +					regulator-max-microvolt = <1000000>;
> +					regulator-boot-on;
> +					regulator-always-on;
> +					ams,enable-tracking;
> +				};
> +
> +				vdd_run_cam: ldo4 {
> +					regulator-name = "+3.3V_RUN_CAM";
> +					regulator-min-microvolt = <2800000>;
> +					regulator-max-microvolt = <2800000>;
> +				};
> +
> +				ldo5 {
> +					regulator-name = "+1.2V_RUN_CAM_FRONT";
> +					regulator-min-microvolt = <1200000>;
> +					regulator-max-microvolt = <1200000>;
> +				};
> +
> +				vddio_sdmmc3: ldo6 {
> +					regulator-name = "+VDDIO_SDMMC3";
> +					regulator-min-microvolt = <1800000>;
> +					regulator-max-microvolt = <3300000>;
> +				};
> +
> +				ldo7 {
> +					regulator-name = "+1.05V_RUN_CAM_REAR";
> +					regulator-min-microvolt = <1050000>;
> +					regulator-max-microvolt = <1050000>;
> +				};
> +
> +				ldo9 {
> +					regulator-name = "+2.8V_RUN_TOUCH";
> +					regulator-min-microvolt = <2800000>;
> +					regulator-max-microvolt = <2800000>;
> +				};
> +
> +				ldo10 {
> +					regulator-name = "+2.8V_RUN_CAM_AF";
> +					regulator-min-microvolt = <2800000>;
> +					regulator-max-microvolt = <2800000>;
> +				};
> +
> +				ldo11 {
> +					regulator-name = "+1.8V_RUN_VPP_FUSE";
> +					regulator-min-microvolt = <1800000>;
> +					regulator-max-microvolt = <1800000>;
> +				};
> +			};
> +		};
> +	};
> +
> +	spi@0,7000d400 {
> +		status = "okay";
> +
> +		cros_ec: cros-ec@0 {
> +			compatible = "google,cros-ec-spi";
> +			spi-max-frequency = <3000000>;
> +			interrupt-parent = <&gpio>;
> +			interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
> +			reg = <0>;
> +
> +			google,cros-ec-spi-msg-delay = <2000>;
> +
> +			i2c-tunnel {
> +				compatible = "google,cros-ec-i2c-tunnel";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				google,remote-bus = <0>;
> +
> +				charger: bq24735@9 {
> +					compatible = "ti,bq24735";
> +					reg = <0x9>;
> +					interrupt-parent = <&gpio>;
> +					interrupts = <TEGRA_GPIO(J, 0)
> +							GPIO_ACTIVE_HIGH>;
> +					ti,ac-detect-gpios = <&gpio
> +							TEGRA_GPIO(J, 0)
> +							GPIO_ACTIVE_HIGH>;
> +				};
> +
> +				battery: sbs-battery@b {
> +					compatible = "sbs,sbs-battery";
> +					reg = <0xb>;
> +					sbs,i2c-retry-count = <2>;
> +					sbs,poll-retry-count = <10>;
> +					power-supplies = <&charger>;
> +				};
> +			};
> +		};
> +	};
> +
> +	spi@0,7000da00 {
> +		status = "okay";
> +		spi-max-frequency = <25000000>;
> +
> +		flash@0 {
> +			compatible = "winbond,w25q32dw";
> +			reg = <0>;
> +		};
> +	};
> +
> +	pmc@0,7000e400 {
> +		nvidia,invert-interrupt;
> +		nvidia,suspend-mode = <0>;
> +		nvidia,cpu-pwr-good-time = <500>;
> +		nvidia,cpu-pwr-off-time = <300>;
> +		nvidia,core-pwr-good-time = <641 3845>;
> +		nvidia,core-pwr-off-time = <61036>;
> +		nvidia,core-power-req-active-high;
> +		nvidia,sys-clock-req-active-high;
> +	};
> +
> +	hda@0,70030000 {
> +		status = "okay";
> +	};
> +
> +	sdhci@0,700b0000 { /* WiFi/BT on this bus */
> +		status = "okay";
> +		power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
> +		bus-width = <4>;
> +		no-1-8-v;
> +		non-removable;
> +	};
> +
> +	sdhci@0,700b0400 { /* SD Card on this bus */
> +		status = "okay";
> +		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
> +		power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
> +		wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
> +		bus-width = <4>;
> +		no-1-8-v;
> +		vqmmc-supply = <&vddio_sdmmc3>;
> +	};
> +
> +	sdhci@0,700b0600 { /* eMMC on this bus */
> +		status = "okay";
> +		bus-width = <8>;
> +		no-1-8-v;
> +		non-removable;
> +	};
> +
> +	ahub@0,70300000 {
> +		i2s@0,70301100 {
> +			status = "okay";
> +		};
> +	};
> +
> +	usb@0,7d000000 { /* Rear external USB port. */
> +		status = "okay";
> +	};
> +
> +	usb-phy@0,7d000000 {
> +		status = "okay";
> +		vbus-supply = <&vdd_usb1_vbus>;
> +	};
> +
> +	usb@0,7d004000 { /* Internal webcam. */
> +		status = "okay";
> +	};
> +
> +	usb-phy@0,7d004000 {
> +		status = "okay";
> +		vbus-supply = <&vdd_run_cam>;
> +	};
> +
> +	usb@0,7d008000 { /* Left external USB port. */
> +		status = "okay";
> +	};
> +
> +	usb-phy@0,7d008000 {
> +		status = "okay";
> +		vbus-supply = <&vdd_usb3_vbus>;
> +	};
> +
> +	backlight: backlight {
> +		compatible = "pwm-backlight";
> +
> +		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
> +		power-supply = <&vdd_led>;
> +		pwms = <&pwm 1 1000000>;
> +
> +		default-brightness-level = <224>;
> +		brightness-levels =
> +			<  0   1   2   3   4   5   6   7
> +			   8   9  10  11  12  13  14  15
> +			  16  17  18  19  20  21  22  23
> +			  24  25  26  27  28  29  30  31
> +			  32  33  34  35  36  37  38  39
> +			  40  41  42  43  44  45  46  47
> +			  48  49  50  51  52  53  54  55
> +			  56  57  58  59  60  61  62  63
> +			  64  65  66  67  68  69  70  71
> +			  72  73  74  75  76  77  78  79
> +			  80  81  82  83  84  85  86  87
> +			  88  89  90  91  92  93  94  95
> +			  96  97  98  99 100 101 102 103
> +			 104 105 106 107 108 109 110 111
> +			 112 113 114 115 116 117 118 119
> +			 120 121 122 123 124 125 126 127
> +			 128 129 130 131 132 133 134 135
> +			 136 137 138 139 140 141 142 143
> +			 144 145 146 147 148 149 150 151
> +			 152 153 154 155 156 157 158 159
> +			 160 161 162 163 164 165 166 167
> +			 168 169 170 171 172 173 174 175
> +			 176 177 178 179 180 181 182 183
> +			 184 185 186 187 188 189 190 191
> +			 192 193 194 195 196 197 198 199
> +			 200 201 202 203 204 205 206 207
> +			 208 209 210 211 212 213 214 215
> +			 216 217 218 219 220 221 222 223
> +			 224 225 226 227 228 229 230 231
> +			 232 233 234 235 236 237 238 239
> +			 240 241 242 243 244 245 246 247
> +			 248 249 250 251 252 253 254 255
> +			 256>;
> +	};
> +
> +	clocks {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		clk32k_in: clock@0 {
> +			compatible = "fixed-clock";
> +			reg = <0>;
> +			#clock-cells = <0>;
> +			clock-frequency = <32768>;
> +		};
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +
> +		lid {
> +			label = "Lid";
> +			gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
> +			linux,input-type = <5>;
> +			linux,code = <KEY_RESERVED>;
> +			debounce-interval = <1>;
> +			gpio-key,wakeup;
> +		};
> +
> +		power {
> +			label = "Power";
> +			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_POWER>;
> +			debounce-interval = <30>;
> +			gpio-key,wakeup;
> +		};
> +	};
> +
> +	panel: panel {
> +		compatible = "auo,b133xtn01";
> +
> +		backlight = <&backlight>;
> +		ddc-i2c-bus = <&dpaux>;
> +	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		vdd_mux: regulator@0 {
> +			compatible = "regulator-fixed";
> +			reg = <0>;
> +			regulator-name = "+VDD_MUX";
> +			regulator-min-microvolt = <12000000>;
> +			regulator-max-microvolt = <12000000>;
> +			regulator-always-on;
> +			regulator-boot-on;
> +		};
> +
> +		vdd_5v0_sys: regulator@1 {overriding where needed

Stray text after '{'?

Regards,
Andreas

> +			compatible = "regulator-fixed";
> +			reg = <1>;
> +			regulator-name = "+5V_SYS";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			regulator-always-on;
> +			regulator-boot-on;
> +			vin-supply = <&vdd_mux>;
> +		};
> +
> +		vdd_3v3_sys: regulator@2 {
> +			compatible = "regulator-fixed";
> +			reg = <2>;
> +			regulator-name = "+3.3V_SYS";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +			regulator-boot-on;
> +			vin-supply = <&vdd_mux>;
> +		};
> +
> +		vdd_3v3_run: regulator@3 {
> +			compatible = "regulator-fixed";
> +			reg = <3>;
> +			regulator-name = "+3.3V_RUN";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +			regulator-boot-on;
> +			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +			vin-supply = <&vdd_3v3_sys>;
> +		};
> +
> +		vdd_3v3_hdmi: regulator@4 {
> +			compatible = "regulator-fixed";
> +			reg = <4>;
> +			regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			vin-supply = <&vdd_3v3_run>;
> +		};
> +
> +		vdd_led: regulator@5 {
> +			compatible = "regulator-fixed";
> +			reg = <5>;
> +			regulator-name = "+VDD_LED";
> +			gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +			vin-supply = <&vdd_mux>;
> +		};
> +
> +		vdd_5v0_ts: regulator@6 {
> +			compatible = "regulator-fixed";
> +			reg = <6>;
> +			regulator-name = "+5V_VDD_TS_SW";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			regulator-boot-on;
> +			gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +			vin-supply = <&vdd_5v0_sys>;
> +		};
> +
> +		vdd_usb1_vbus: regulator@7 {
> +			compatible = "regulator-fixed";
> +			reg = <7>;
> +			regulator-name = "+5V_USB_HS";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +			gpio-open-drain;
> +			vin-supply = <&vdd_5v0_sys>;
> +		};
> +
> +		vdd_usb3_vbus: regulator@8 {
> +			compatible = "regulator-fixed";
> +			reg = <8>;
> +			regulator-name = "+5V_USB_SS";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +			gpio-open-drain;
> +			vin-supply = <&vdd_5v0_sys>;
> +		};
> +
> +		vdd_3v3_panel: regulator@9 {
> +			compatible = "regulator-fixed";
> +			reg = <9>;
> +			regulator-name = "+3.3V_PANEL";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +			vin-supply = <&vdd_3v3_run>;
> +		};
> +
> +		vdd_3v3_lp0: regulator@10 {
> +			compatible = "regulator-fixed";
> +			reg = <10>;
> +			regulator-name = "+3.3V_LP0";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			/*
> +			 * TODO: find a way to wire this up with the USB EHCI
> +			 * controllers so that it can be enabled on demand.
> +			 */
> +			regulator-always-on;
> +			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +			vin-supply = <&vdd_3v3_sys>;
> +		};
> +
> +		vdd_hdmi_pll: regulator@11 {
> +			compatible = "regulator-fixed";
> +			reg = <11>;
> +			regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
> +			regulator-min-microvolt = <1050000>;
> +			regulator-max-microvolt = <1050000>;
> +			gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
> +			vin-supply = <&vdd_1v05_run>;
> +		};
> +
> +		vdd_5v0_hdmi: regulator@12 {
> +			compatible = "regulator-fixed";
> +			reg = <12>;
> +			regulator-name = "+5V_HDMI_CON";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +			vin-supply = <&vdd_5v0_sys>;
> +		};
> +	};
> +
> +	sound {
> +		compatible = "nvidia,tegra-audio-max98090-nyan-big",
> +			     "nvidia,tegra-audio-max98090";
> +		nvidia,model = "Acer Chromebook 13";
> +
> +		nvidia,audio-routing =
> +			"Headphones", "HPR",
> +			"Headphones", "HPL",
> +			"Speakers", "SPKR",
> +			"Speakers", "SPKL",
> +			"Mic Jack", "MICBIAS",
> +			"DMICL", "Int Mic",
> +			"DMICR", "Int Mic",
> +			"IN34", "Mic Jack";
> +
> +		nvidia,i2s-controller = <&tegra_i2s1>;
> +		nvidia,audio-codec = <&acodec>;
> +
> +		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
> +			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
> +			 <&tegra_car TEGRA124_CLK_EXTERN1>;
> +		clock-names = "pll_a", "pll_a_out0", "mclk";
> +
> +		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
> +	};
> +};
> +
> +#include "cros-ec-keyboard.dtsi"
>

Stephen Warren Aug. 18, 2014, 4:10 p.m. UTC | #2

On 08/16/2014 09:20 AM, Andreas Färber wrote:
> Hi,
>
> Am 13.08.2014 21:14, schrieb Dylan Reid:
>> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
>> processor and is similar to the Venice2 reference platform.
>>
>> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
>> and work on the 1266x768 models.  The HD models haven't yet been
>> tested.
>>
>> WiFi does not work yet, it needs at least some PMIC changes to enable
>> the 32k clock.
>>
>> The elan trackpad is not yet functional but hopefully will be soon as
>> there are patches under review.
>>
>> There is also an issue on reboot because the TPM isn't reset.  It will
>> cause the stock firmware to enter recovery mode.  This can be worked
>> around by an EC-reset, press the refresh and power keys at the same
>> time.

>> diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
>> new file mode 100644
>> index 0000000..79f1852
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
>> @@ -0,0 +1,1136 @@
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/input/input.h>
>> +#include "tegra124.dtsi"
>> +
>> +/ {
>> +	model = "Acer Chromebook 13";
>> +	compatible = "google,nyan-big", "nvidia,tegra124";
>
> In light of v1 and the above commit message referring to this as Google
> Big, shouldn't this be "google,big", "nvidia,tegra124" and optionally
> "google,nyan" as secondary string, independent of the new file name?

Despite this board having been derived from Nyan, it isn't Nyan, so I 
don't think Nyan should be part of any compatible value, nor a separate 
compatible value.

>> +	pinmux: pinmux@0,70000868 {
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&pinmux_default>;
>> +
>> +		pinmux_default: common {
>> +			dap_mclk1_pw4 {
>
> Any need to have the nodes this way? Shouldn't this rather be
> dap-mclk1-pw4 as node name by conventions, with a dap_mclk1_pw4 label
> for referencing if needed? Same below, obviously.

Underscores are consistent with at least all the other Tegra DTs, so I 
think this is best as is.

>> +	pwm: pwm@0,7000a000 {
>
> Add the label to the .dtsi where the node is first declared? Then you
> can override it the safer &pwm { ... }; way. Same for all other nodes
> being extended/overridden here - that's what your colleagues requested
> for Spring. It'll help with the 80 char limit further below by reducing
> indentation.

We certainly do have the pwm label in *.dtsi for other SoCs, so we 
should probably move the label there.

Using the &pwm {} syntax would be inconsistent with all the other Tegra 
DTs, and isn't really any safer; the HW isn't going to change, so once 
this is written, it should continue to "just work".

Andreas Färber Aug. 18, 2014, 5:03 p.m. UTC | #3

Am 18.08.2014 18:10, schrieb Stephen Warren:
> On 08/16/2014 09:20 AM, Andreas Färber wrote:
>> Am 13.08.2014 21:14, schrieb Dylan Reid:
>>> +    pinmux: pinmux@0,70000868 {
>>> +        pinctrl-names = "default";
>>> +        pinctrl-0 = <&pinmux_default>;
>>> +
>>> +        pinmux_default: common {
>>> +            dap_mclk1_pw4 {
>>
>> Any need to have the nodes this way? Shouldn't this rather be
>> dap-mclk1-pw4 as node name by conventions, with a dap_mclk1_pw4 label
>> for referencing if needed? Same below, obviously.
> 
> Underscores are consistent with at least all the other Tegra DTs, so I
> think this is best as is.
> 
>>> +    pwm: pwm@0,7000a000 {
>>
>> Add the label to the .dtsi where the node is first declared? Then you
>> can override it the safer &pwm { ... }; way. Same for all other nodes
>> being extended/overridden here - that's what your colleagues requested
>> for Spring. It'll help with the 80 char limit further below by reducing
>> indentation.
> 
> We certainly do have the pwm label in *.dtsi for other SoCs, so we
> should probably move the label there.
> 
> Using the &pwm {} syntax would be inconsistent with all the other Tegra
> DTs, and isn't really any safer; the HW isn't going to change, so once
> this is written, it should continue to "just work".

For exactly those consistency reasons I was asked to refactor the whole
set of exynos5250-*.dts files despite having no relation to them -
turning my 1 .dts patch into a large series that still isn't applied...

It's funny and disappointing that every Linux maintainer seems to have
their own conventions, and not even the Google Chrome people can agree
on a common style or live up to what they ask of others.

As for &pwm {}, I understood it's "safer" in that mismatches in the node
name will lead to compilation errors rather than silent runtime misbehavior.

Regards,
Andreas

Andrew Bresticker Aug. 18, 2014, 11:05 p.m. UTC | #4

> WiFi does not work yet, it needs at least some PMIC changes to enable
> the 32k clock.

In addition to getting the PMIC to generate the 32k clock at 1.8V
(instead of the 5V it's operating at now), you'll also need...

> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts

> +                       sdmmc1_clk_pz0 {
> +                               nvidia,pins = "sdmmc1_clk_pz0";
> +                               nvidia,function = "sdmmc1";
> +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;

... to turn on the input enable for the SD clock pin on the SDIO
interface.  Unfortunately that still isn't sufficient to get WiFi
working as SDIO commands are still timing out.  But the mwifiex card
is at least attempting to probe now.

> +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +                       };

Andrew Bresticker Aug. 18, 2014, 11:24 p.m. UTC | #5

On Mon, Aug 18, 2014 at 9:10 AM, Stephen Warren <[e-mail]> wrote:
> On 08/16/2014 09:20 AM, Andreas Färber wrote:
>>
>> Hi,
>>
>> Am 13.08.2014 21:14, schrieb Dylan Reid:
>>>
>>> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
>>> processor and is similar to the Venice2 reference platform.
>>>
>>> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
>>> and work on the 1266x768 models.  The HD models haven't yet been
>>> tested.
>>>
>>> WiFi does not work yet, it needs at least some PMIC changes to enable
>>> the 32k clock.
>>>
>>> The elan trackpad is not yet functional but hopefully will be soon as
>>> there are patches under review.
>>>
>>> There is also an issue on reboot because the TPM isn't reset.  It will
>>> cause the stock firmware to enter recovery mode.  This can be worked
>>> around by an EC-reset, press the refresh and power keys at the same
>>> time.
>
>
>>> diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts
>>> b/arch/arm/boot/dts/tegra124-nyan-big.dts
>>> new file mode 100644
>>> index 0000000..79f1852
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
>>> @@ -0,0 +1,1136 @@
>>> +/dts-v1/;
>>> +
>>> +#include <dt-bindings/input/input.h>
>>> +#include "tegra124.dtsi"
>>> +
>>> +/ {
>>> +       model = "Acer Chromebook 13";
>>> +       compatible = "google,nyan-big", "nvidia,tegra124";
>>
>>
>> In light of v1 and the above commit message referring to this as Google
>> Big, shouldn't this be "google,big", "nvidia,tegra124" and optionally
>> "google,nyan" as secondary string, independent of the new file name?
>
>
> Despite this board having been derived from Nyan, it isn't Nyan, so I don't
> think Nyan should be part of any compatible value, nor a separate compatible
> value.

"google,nyan-big" is the compatible string that the bootloader on
these devices looks for.  It's also the convention we are now using
for our ARM devices, as Olof has already mentioned.

Stephen Warren Aug. 18, 2014, 11:43 p.m. UTC | #6

On 08/18/2014 05:24 PM, Andrew Bresticker wrote:
> On Mon, Aug 18, 2014 at 9:10 AM, Stephen Warren <[e-mail]> wrote:
>> On 08/16/2014 09:20 AM, Andreas Färber wrote:
>>>
>>> Hi,
>>>
>>> Am 13.08.2014 21:14, schrieb Dylan Reid:
>>>>
>>>> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
>>>> processor and is similar to the Venice2 reference platform.
>>>>
>>>> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
>>>> and work on the 1266x768 models.  The HD models haven't yet been
>>>> tested.
>>>>
>>>> WiFi does not work yet, it needs at least some PMIC changes to enable
>>>> the 32k clock.
>>>>
>>>> The elan trackpad is not yet functional but hopefully will be soon as
>>>> there are patches under review.
>>>>
>>>> There is also an issue on reboot because the TPM isn't reset.  It will
>>>> cause the stock firmware to enter recovery mode.  This can be worked
>>>> around by an EC-reset, press the refresh and power keys at the same
>>>> time.
>>
>>
>>>> diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>> b/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>> new file mode 100644
>>>> index 0000000..79f1852
>>>> --- /dev/null
>>>> +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>> @@ -0,0 +1,1136 @@
>>>> +/dts-v1/;
>>>> +
>>>> +#include <dt-bindings/input/input.h>
>>>> +#include "tegra124.dtsi"
>>>> +
>>>> +/ {
>>>> +       model = "Acer Chromebook 13";
>>>> +       compatible = "google,nyan-big", "nvidia,tegra124";
>>>
>>>
>>> In light of v1 and the above commit message referring to this as Google
>>> Big, shouldn't this be "google,big", "nvidia,tegra124" and optionally
>>> "google,nyan" as secondary string, independent of the new file name?
>>
>>
>> Despite this board having been derived from Nyan, it isn't Nyan, so I don't
>> think Nyan should be part of any compatible value, nor a separate compatible
>> value.
>
> "google,nyan-big" is the compatible string that the bootloader on
> these devices looks for.  It's also the convention we are now using
> for our ARM devices, as Olof has already mentioned.

I don't understand "that the bootloader looks for"; why is the 
bootloader doing anything w.r.t the compatible value in the DT that's 
passed to the kernel.

Olof also mentioned that if I had any better ideas on file naming, I 
should point them out. As I mentioned in response, there's zero need for 
all the files or compatible values to have "nyan" in them in order to 
include any common .dtsi file, which was the justification for having 
"nyan" in the filename, IIRC.

Again, this board *isn't* Nyan, so it should pretend that it is.

Andrew Bresticker Aug. 19, 2014, 12:11 a.m. UTC | #7

On Mon, Aug 18, 2014 at 4:43 PM, Stephen Warren <[e-mail]> wrote:
> On 08/18/2014 05:24 PM, Andrew Bresticker wrote:
>>
>> On Mon, Aug 18, 2014 at 9:10 AM, Stephen Warren <[e-mail]>
>> wrote:
>>>
>>> On 08/16/2014 09:20 AM, Andreas Färber wrote:
>>>>
>>>>
>>>> Hi,
>>>>
>>>> Am 13.08.2014 21:14, schrieb Dylan Reid:
>>>>>
>>>>>
>>>>> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
>>>>> processor and is similar to the Venice2 reference platform.
>>>>>
>>>>> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
>>>>> and work on the 1266x768 models.  The HD models haven't yet been
>>>>> tested.
>>>>>
>>>>> WiFi does not work yet, it needs at least some PMIC changes to enable
>>>>> the 32k clock.
>>>>>
>>>>> The elan trackpad is not yet functional but hopefully will be soon as
>>>>> there are patches under review.
>>>>>
>>>>> There is also an issue on reboot because the TPM isn't reset.  It will
>>>>> cause the stock firmware to enter recovery mode.  This can be worked
>>>>> around by an EC-reset, press the refresh and power keys at the same
>>>>> time.
>>>
>>>
>>>
>>>>> diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>>> b/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>>> new file mode 100644
>>>>> index 0000000..79f1852
>>>>> --- /dev/null
>>>>> +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>>> @@ -0,0 +1,1136 @@
>>>>> +/dts-v1/;
>>>>> +
>>>>> +#include <dt-bindings/input/input.h>
>>>>> +#include "tegra124.dtsi"
>>>>> +
>>>>> +/ {
>>>>> +       model = "Acer Chromebook 13";
>>>>> +       compatible = "google,nyan-big", "nvidia,tegra124";
>>>>
>>>>
>>>>
>>>> In light of v1 and the above commit message referring to this as Google
>>>> Big, shouldn't this be "google,big", "nvidia,tegra124" and optionally
>>>> "google,nyan" as secondary string, independent of the new file name?
>>>
>>>
>>>
>>> Despite this board having been derived from Nyan, it isn't Nyan, so I
>>> don't
>>> think Nyan should be part of any compatible value, nor a separate
>>> compatible
>>> value.
>>
>>
>> "google,nyan-big" is the compatible string that the bootloader on
>> these devices looks for.  It's also the convention we are now using
>> for our ARM devices, as Olof has already mentioned.
>
>
> I don't understand "that the bootloader looks for"; why is the bootloader
> doing anything w.r.t the compatible value in the DT that's passed to the
> kernel.

The ChromeOS bootloader ("depthcharge") boots FIT images and selects
the appropriate device-tree from the image based on the compatible
string.  On Big boards, it looks for "google,nyan-big".  This only
becomes an issue if there are multiple device-trees in the FIT image.
If there's only a single configuration (or you chain-load U-Boot),
then the bootloader will boot with that configuration.  If you build a
kernel image in the ChromiumOS environment, however, you'll end up
with multiple device-trees (all those built by the kernel config at
least) in the FIT image - this is what allows us to boot the same
binary on different boards.

Stephen Warren Aug. 19, 2014, 9:47 p.m. UTC | #8

On 08/18/2014 06:11 PM, Andrew Bresticker wrote:
> On Mon, Aug 18, 2014 at 4:43 PM, Stephen Warren <[e-mail]> wrote:
>> On 08/18/2014 05:24 PM, Andrew Bresticker wrote:
>>>
>>> On Mon, Aug 18, 2014 at 9:10 AM, Stephen Warren <[e-mail]>
>>> wrote:
>>>>
>>>> On 08/16/2014 09:20 AM, Andreas Färber wrote:
>>>>>
>>>>>
>>>>> Hi,
>>>>>
>>>>> Am 13.08.2014 21:14, schrieb Dylan Reid:
>>>>>>
>>>>>>
>>>>>> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
>>>>>> processor and is similar to the Venice2 reference platform.
>>>>>>
>>>>>> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
>>>>>> and work on the 1266x768 models.  The HD models haven't yet been
>>>>>> tested.
>>>>>>
>>>>>> WiFi does not work yet, it needs at least some PMIC changes to enable
>>>>>> the 32k clock.
>>>>>>
>>>>>> The elan trackpad is not yet functional but hopefully will be soon as
>>>>>> there are patches under review.
>>>>>>
>>>>>> There is also an issue on reboot because the TPM isn't reset.  It will
>>>>>> cause the stock firmware to enter recovery mode.  This can be worked
>>>>>> around by an EC-reset, press the refresh and power keys at the same
>>>>>> time.
>>>>
>>>>
>>>>
>>>>>> diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>>>> b/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>>>> new file mode 100644
>>>>>> index 0000000..79f1852
>>>>>> --- /dev/null
>>>>>> +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>>>> @@ -0,0 +1,1136 @@
>>>>>> +/dts-v1/;
>>>>>> +
>>>>>> +#include <dt-bindings/input/input.h>
>>>>>> +#include "tegra124.dtsi"
>>>>>> +
>>>>>> +/ {
>>>>>> +       model = "Acer Chromebook 13";
>>>>>> +       compatible = "google,nyan-big", "nvidia,tegra124";
>>>>>
>>>>>
>>>>>
>>>>> In light of v1 and the above commit message referring to this as Google
>>>>> Big, shouldn't this be "google,big", "nvidia,tegra124" and optionally
>>>>> "google,nyan" as secondary string, independent of the new file name?
>>>>
>>>>
>>>>
>>>> Despite this board having been derived from Nyan, it isn't Nyan, so I
>>>> don't
>>>> think Nyan should be part of any compatible value, nor a separate
>>>> compatible
>>>> value.
>>>
>>>
>>> "google,nyan-big" is the compatible string that the bootloader on
>>> these devices looks for.  It's also the convention we are now using
>>> for our ARM devices, as Olof has already mentioned.
>>
>> I don't understand "that the bootloader looks for"; why is the bootloader
>> doing anything w.r.t the compatible value in the DT that's passed to the
>> kernel.
>
> The ChromeOS bootloader ("depthcharge") boots FIT images and selects
> the appropriate device-tree from the image based on the compatible
> string.  On Big boards, it looks for "google,nyan-big".  This only
> becomes an issue if there are multiple device-trees in the FIT image.
> If there's only a single configuration (or you chain-load U-Boot),
> then the bootloader will boot with that configuration.  If you build a
> kernel image in the ChromiumOS environment, however, you'll end up
> with multiple device-trees (all those built by the kernel config at
> least) in the FIT image - this is what allows us to boot the same
> binary on different boards.

This just makes me dislike FIT (and DT ABIs) even more, although I 
suppose the same issue would arise if the DTBs were stored in separate 
files and looked up by filename.

I have to say this sucks, because it means that a downstream bootloader 
is imposing an ABI on the mainline kernel without a chance to fix things 
during upstreaming. For all other boards, we've concentrated on mainline 
U-Boot as the bootloader precisely so that strange behaviour of our 
downstream product kernels don't force the hand of the mainline kernel 
design.

Still, I suppose I have no choice but to drop my objection here.

Thierry Reding Aug. 20, 2014, 5:36 a.m. UTC | #9

On Tue, Aug 19, 2014 at 03:47:41PM -0600, Stephen Warren wrote:
> On 08/18/2014 06:11 PM, Andrew Bresticker wrote:
> >On Mon, Aug 18, 2014 at 4:43 PM, Stephen Warren <[e-mail]> wrote:
> >>On 08/18/2014 05:24 PM, Andrew Bresticker wrote:
> >>>
> >>>On Mon, Aug 18, 2014 at 9:10 AM, Stephen Warren <[e-mail]>
> >>>wrote:
> >>>>
> >>>>On 08/16/2014 09:20 AM, Andreas Färber wrote:
> >>>>>
> >>>>>
> >>>>>Hi,
> >>>>>
> >>>>>Am 13.08.2014 21:14, schrieb Dylan Reid:
> >>>>>>
> >>>>>>
> >>>>>>The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
> >>>>>>processor and is similar to the Venice2 reference platform.
> >>>>>>
> >>>>>>The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
> >>>>>>and work on the 1266x768 models.  The HD models haven't yet been
> >>>>>>tested.
> >>>>>>
> >>>>>>WiFi does not work yet, it needs at least some PMIC changes to enable
> >>>>>>the 32k clock.
> >>>>>>
> >>>>>>The elan trackpad is not yet functional but hopefully will be soon as
> >>>>>>there are patches under review.
> >>>>>>
> >>>>>>There is also an issue on reboot because the TPM isn't reset.  It will
> >>>>>>cause the stock firmware to enter recovery mode.  This can be worked
> >>>>>>around by an EC-reset, press the refresh and power keys at the same
> >>>>>>time.
> >>>>
> >>>>
> >>>>
> >>>>>>diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts
> >>>>>>b/arch/arm/boot/dts/tegra124-nyan-big.dts
> >>>>>>new file mode 100644
> >>>>>>index 0000000..79f1852
> >>>>>>--- /dev/null
> >>>>>>+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
> >>>>>>@@ -0,0 +1,1136 @@
> >>>>>>+/dts-v1/;
> >>>>>>+
> >>>>>>+#include <dt-bindings/input/input.h>
> >>>>>>+#include "tegra124.dtsi"
> >>>>>>+
> >>>>>>+/ {
> >>>>>>+       model = "Acer Chromebook 13";
> >>>>>>+       compatible = "google,nyan-big", "nvidia,tegra124";
> >>>>>
> >>>>>
> >>>>>
> >>>>>In light of v1 and the above commit message referring to this as Google
> >>>>>Big, shouldn't this be "google,big", "nvidia,tegra124" and optionally
> >>>>>"google,nyan" as secondary string, independent of the new file name?
> >>>>
> >>>>
> >>>>
> >>>>Despite this board having been derived from Nyan, it isn't Nyan, so I
> >>>>don't
> >>>>think Nyan should be part of any compatible value, nor a separate
> >>>>compatible
> >>>>value.
> >>>
> >>>
> >>>"google,nyan-big" is the compatible string that the bootloader on
> >>>these devices looks for.  It's also the convention we are now using
> >>>for our ARM devices, as Olof has already mentioned.
> >>
> >>I don't understand "that the bootloader looks for"; why is the bootloader
> >>doing anything w.r.t the compatible value in the DT that's passed to the
> >>kernel.
> >
> >The ChromeOS bootloader ("depthcharge") boots FIT images and selects
> >the appropriate device-tree from the image based on the compatible
> >string.  On Big boards, it looks for "google,nyan-big".  This only
> >becomes an issue if there are multiple device-trees in the FIT image.
> >If there's only a single configuration (or you chain-load U-Boot),
> >then the bootloader will boot with that configuration.  If you build a
> >kernel image in the ChromiumOS environment, however, you'll end up
> >with multiple device-trees (all those built by the kernel config at
> >least) in the FIT image - this is what allows us to boot the same
> >binary on different boards.
> 
> This just makes me dislike FIT (and DT ABIs) even more, although I suppose
> the same issue would arise if the DTBs were stored in separate files and
> looked up by filename.
> 
> I have to say this sucks, because it means that a downstream bootloader is
> imposing an ABI on the mainline kernel without a chance to fix things during
> upstreaming. For all other boards, we've concentrated on mainline U-Boot as
> the bootloader precisely so that strange behaviour of our downstream product
> kernels don't force the hand of the mainline kernel design.
> 
> Still, I suppose I have no choice but to drop my objection here.

Do you? We reject things all the time if they're considered not good
enough during upstreaming. The whole DT ABI debate in fact explicitly
resulted in the decision not to take any of the downstream components
into consideration when upstreaming. ABI stability only counts for
things that we've supported in one of the final releases.

Thierry

Olof Johansson Aug. 20, 2014, 1:29 p.m. UTC | #10

On Mon, Aug 18, 2014 at 4:43 PM, Stephen Warren <[e-mail]> wrote:
> On 08/18/2014 05:24 PM, Andrew Bresticker wrote:
>>
>> On Mon, Aug 18, 2014 at 9:10 AM, Stephen Warren <[e-mail]>
>> wrote:
>>>
>>> On 08/16/2014 09:20 AM, Andreas Färber wrote:
>>>>
>>>>
>>>> Hi,
>>>>
>>>> Am 13.08.2014 21:14, schrieb Dylan Reid:
>>>>>
>>>>>
>>>>> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
>>>>> processor and is similar to the Venice2 reference platform.
>>>>>
>>>>> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
>>>>> and work on the 1266x768 models.  The HD models haven't yet been
>>>>> tested.
>>>>>
>>>>> WiFi does not work yet, it needs at least some PMIC changes to enable
>>>>> the 32k clock.
>>>>>
>>>>> The elan trackpad is not yet functional but hopefully will be soon as
>>>>> there are patches under review.
>>>>>
>>>>> There is also an issue on reboot because the TPM isn't reset.  It will
>>>>> cause the stock firmware to enter recovery mode.  This can be worked
>>>>> around by an EC-reset, press the refresh and power keys at the same
>>>>> time.
>>>
>>>
>>>
>>>>> diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>>> b/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>>> new file mode 100644
>>>>> index 0000000..79f1852
>>>>> --- /dev/null
>>>>> +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>>> @@ -0,0 +1,1136 @@
>>>>> +/dts-v1/;
>>>>> +
>>>>> +#include <dt-bindings/input/input.h>
>>>>> +#include "tegra124.dtsi"
>>>>> +
>>>>> +/ {
>>>>> +       model = "Acer Chromebook 13";
>>>>> +       compatible = "google,nyan-big", "nvidia,tegra124";
>>>>
>>>>
>>>>
>>>> In light of v1 and the above commit message referring to this as Google
>>>> Big, shouldn't this be "google,big", "nvidia,tegra124" and optionally
>>>> "google,nyan" as secondary string, independent of the new file name?
>>>
>>>
>>>
>>> Despite this board having been derived from Nyan, it isn't Nyan, so I
>>> don't
>>> think Nyan should be part of any compatible value, nor a separate
>>> compatible
>>> value.
>>
>>
>> "google,nyan-big" is the compatible string that the bootloader on
>> these devices looks for.  It's also the convention we are now using
>> for our ARM devices, as Olof has already mentioned.
>
>
> I don't understand "that the bootloader looks for"; why is the bootloader
> doing anything w.r.t the compatible value in the DT that's passed to the
> kernel.
>
> Olof also mentioned that if I had any better ideas on file naming, I should
> point them out. As I mentioned in response, there's zero need for all the
> files or compatible values to have "nyan" in them in order to include any
> common .dtsi file, which was the justification for having "nyan" in the
> filename, IIRC.

Yes, I asked for input, not full veto on things that you happened to
not like. I also didn't say that we could change everything depending
on said input -- some of them might be longer-term changes that we'll
have to consider for a future project, etc. Some of them we might even
disagree on! (see below).

> Again, this board *isn't* Nyan, so it should pretend that it is.

It is a derivative design of the nyan reference platform, and it is
compatible with it. It is perfectly fine to claim to be compatible
with it. I'm sorry, but you're just wrong here.


-Olof

Olof Johansson Aug. 20, 2014, 1:37 p.m. UTC | #11

On Tue, Aug 19, 2014 at 2:47 PM, Stephen Warren <[e-mail]> wrote:
> On 08/18/2014 06:11 PM, Andrew Bresticker wrote:
>>
>> On Mon, Aug 18, 2014 at 4:43 PM, Stephen Warren <[e-mail]>
>> wrote:
>>>
>>> On 08/18/2014 05:24 PM, Andrew Bresticker wrote:
>>>>
>>>>
>>>> On Mon, Aug 18, 2014 at 9:10 AM, Stephen Warren <[e-mail]>
>>>> wrote:
>>>>>
>>>>>
>>>>> On 08/16/2014 09:20 AM, Andreas Färber wrote:
>>>>>>
>>>>>>
>>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> Am 13.08.2014 21:14, schrieb Dylan Reid:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
>>>>>>> processor and is similar to the Venice2 reference platform.
>>>>>>>
>>>>>>> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
>>>>>>> and work on the 1266x768 models.  The HD models haven't yet been
>>>>>>> tested.
>>>>>>>
>>>>>>> WiFi does not work yet, it needs at least some PMIC changes to enable
>>>>>>> the 32k clock.
>>>>>>>
>>>>>>> The elan trackpad is not yet functional but hopefully will be soon as
>>>>>>> there are patches under review.
>>>>>>>
>>>>>>> There is also an issue on reboot because the TPM isn't reset.  It
>>>>>>> will
>>>>>>> cause the stock firmware to enter recovery mode.  This can be worked
>>>>>>> around by an EC-reset, press the refresh and power keys at the same
>>>>>>> time.
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>>> diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>>>>> b/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>>>>> new file mode 100644
>>>>>>> index 0000000..79f1852
>>>>>>> --- /dev/null
>>>>>>> +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
>>>>>>> @@ -0,0 +1,1136 @@
>>>>>>> +/dts-v1/;
>>>>>>> +
>>>>>>> +#include <dt-bindings/input/input.h>
>>>>>>> +#include "tegra124.dtsi"
>>>>>>> +
>>>>>>> +/ {
>>>>>>> +       model = "Acer Chromebook 13";
>>>>>>> +       compatible = "google,nyan-big", "nvidia,tegra124";
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> In light of v1 and the above commit message referring to this as
>>>>>> Google
>>>>>> Big, shouldn't this be "google,big", "nvidia,tegra124" and optionally
>>>>>> "google,nyan" as secondary string, independent of the new file name?
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> Despite this board having been derived from Nyan, it isn't Nyan, so I
>>>>> don't
>>>>> think Nyan should be part of any compatible value, nor a separate
>>>>> compatible
>>>>> value.
>>>>
>>>>
>>>>
>>>> "google,nyan-big" is the compatible string that the bootloader on
>>>> these devices looks for.  It's also the convention we are now using
>>>> for our ARM devices, as Olof has already mentioned.
>>>
>>>
>>> I don't understand "that the bootloader looks for"; why is the bootloader
>>> doing anything w.r.t the compatible value in the DT that's passed to the
>>> kernel.
>>
>>
>> The ChromeOS bootloader ("depthcharge") boots FIT images and selects
>> the appropriate device-tree from the image based on the compatible
>> string.  On Big boards, it looks for "google,nyan-big".  This only
>> becomes an issue if there are multiple device-trees in the FIT image.
>> If there's only a single configuration (or you chain-load U-Boot),
>> then the bootloader will boot with that configuration.  If you build a
>> kernel image in the ChromiumOS environment, however, you'll end up
>> with multiple device-trees (all those built by the kernel config at
>> least) in the FIT image - this is what allows us to boot the same
>> binary on different boards.
>
>
> This just makes me dislike FIT (and DT ABIs) even more, although I suppose
> the same issue would arise if the DTBs were stored in separate files and
> looked up by filename.

Yes, or stored in separate files and looked up by compatible field.

Do you have a suggestion on a better way to solve it, btw? Definitely
not one of those things we can fix retroactively, but if it works
poorly for you upstream we'll consider improvements if we can for
future products.

I'm not a huge fan of fitImage myself, but it gets the work done.

> I have to say this sucks, because it means that a downstream bootloader is
> imposing an ABI on the mainline kernel without a chance to fix things during
> upstreaming. For all other boards, we've concentrated on mainline U-Boot as
> the bootloader precisely so that strange behaviour of our downstream product
> kernels don't force the hand of the mainline kernel design.
>
> Still, I suppose I have no choice but to drop my objection here.

Thanks for being pragmatic on this one, Stephen!


-Olof

Thierry Reding Aug. 20, 2014, 2:32 p.m. UTC | #12

On Wed, Aug 20, 2014 at 06:29:14AM -0700, Olof Johansson wrote:
> On Mon, Aug 18, 2014 at 4:43 PM, Stephen Warren <[e-mail]> wrote:
[...]
> > Again, this board *isn't* Nyan, so it should pretend that it is.
> 
> It is a derivative design of the nyan reference platform, and it is
> compatible with it. It is perfectly fine to claim to be compatible
> with it. I'm sorry, but you're just wrong here.

I guess that depends a little on how you define compatibility. I had
always assumed that the top-level compatible string would be a sort of
"checksum" over the rest of the content. Which, admittedly, makes it
kind of redundant. Compatibility could mean a lot of things. Does it
mean any kernel/DTB compatible with one device could run on any device
derived from it? Does compatibility mean it needs to provide full
functionality or is it still compatible if it runs at a reduced feature
set but doesn't "break" otherwise?

Thierry

Thierry Reding Aug. 20, 2014, 3:25 p.m. UTC | #13

On Wed, Aug 20, 2014 at 06:37:48AM -0700, Olof Johansson wrote:
> On Tue, Aug 19, 2014 at 2:47 PM, Stephen Warren <[e-mail]> wrote:
> > On 08/18/2014 06:11 PM, Andrew Bresticker wrote:
> >>
> >> On Mon, Aug 18, 2014 at 4:43 PM, Stephen Warren <[e-mail]>
> >> wrote:
> >>>
> >>> On 08/18/2014 05:24 PM, Andrew Bresticker wrote:
> >>>>
> >>>>
> >>>> On Mon, Aug 18, 2014 at 9:10 AM, Stephen Warren <[e-mail]>
> >>>> wrote:
> >>>>>
> >>>>>
> >>>>> On 08/16/2014 09:20 AM, Andreas Färber wrote:
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>> Hi,
> >>>>>>
> >>>>>> Am 13.08.2014 21:14, schrieb Dylan Reid:
> >>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
> >>>>>>> processor and is similar to the Venice2 reference platform.
> >>>>>>>
> >>>>>>> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
> >>>>>>> and work on the 1266x768 models.  The HD models haven't yet been
> >>>>>>> tested.
> >>>>>>>
> >>>>>>> WiFi does not work yet, it needs at least some PMIC changes to enable
> >>>>>>> the 32k clock.
> >>>>>>>
> >>>>>>> The elan trackpad is not yet functional but hopefully will be soon as
> >>>>>>> there are patches under review.
> >>>>>>>
> >>>>>>> There is also an issue on reboot because the TPM isn't reset.  It
> >>>>>>> will
> >>>>>>> cause the stock firmware to enter recovery mode.  This can be worked
> >>>>>>> around by an EC-reset, press the refresh and power keys at the same
> >>>>>>> time.
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>>> diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts
> >>>>>>> b/arch/arm/boot/dts/tegra124-nyan-big.dts
> >>>>>>> new file mode 100644
> >>>>>>> index 0000000..79f1852
> >>>>>>> --- /dev/null
> >>>>>>> +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
> >>>>>>> @@ -0,0 +1,1136 @@
> >>>>>>> +/dts-v1/;
> >>>>>>> +
> >>>>>>> +#include <dt-bindings/input/input.h>
> >>>>>>> +#include "tegra124.dtsi"
> >>>>>>> +
> >>>>>>> +/ {
> >>>>>>> +       model = "Acer Chromebook 13";
> >>>>>>> +       compatible = "google,nyan-big", "nvidia,tegra124";
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>> In light of v1 and the above commit message referring to this as
> >>>>>> Google
> >>>>>> Big, shouldn't this be "google,big", "nvidia,tegra124" and optionally
> >>>>>> "google,nyan" as secondary string, independent of the new file name?
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>> Despite this board having been derived from Nyan, it isn't Nyan, so I
> >>>>> don't
> >>>>> think Nyan should be part of any compatible value, nor a separate
> >>>>> compatible
> >>>>> value.
> >>>>
> >>>>
> >>>>
> >>>> "google,nyan-big" is the compatible string that the bootloader on
> >>>> these devices looks for.  It's also the convention we are now using
> >>>> for our ARM devices, as Olof has already mentioned.
> >>>
> >>>
> >>> I don't understand "that the bootloader looks for"; why is the bootloader
> >>> doing anything w.r.t the compatible value in the DT that's passed to the
> >>> kernel.
> >>
> >>
> >> The ChromeOS bootloader ("depthcharge") boots FIT images and selects
> >> the appropriate device-tree from the image based on the compatible
> >> string.  On Big boards, it looks for "google,nyan-big".  This only
> >> becomes an issue if there are multiple device-trees in the FIT image.
> >> If there's only a single configuration (or you chain-load U-Boot),
> >> then the bootloader will boot with that configuration.  If you build a
> >> kernel image in the ChromiumOS environment, however, you'll end up
> >> with multiple device-trees (all those built by the kernel config at
> >> least) in the FIT image - this is what allows us to boot the same
> >> binary on different boards.
> >
> >
> > This just makes me dislike FIT (and DT ABIs) even more, although I suppose
> > the same issue would arise if the DTBs were stored in separate files and
> > looked up by filename.
> 
> Yes, or stored in separate files and looked up by compatible field.
> 
> Do you have a suggestion on a better way to solve it, btw? Definitely
> not one of those things we can fix retroactively, but if it works
> poorly for you upstream we'll consider improvements if we can for
> future products.
> 
> I'm not a huge fan of fitImage myself, but it gets the work done.

It's been a long time since I've used FIT, but I seem to remember that
it was simply a device tree-based description of a file format. As such
couldn't you add an additional property to the configuration entry that
the bootloader could match on? That would avoid the need to parse an
embedded device tree and it might be useful to keep variants for the
same board in the same FIT image.

Perhaps you can explain a little more what the use-cases are. For
example how are people suppose to run an upstream kernel on one of these
Chromebooks? Do they completely replace one FIT image with another (and
in the process delete or rename the original one)? Or can they simply
add another FIT image that contains the kernel and DTB from upstream? Is
there a way to add new configurations to an existing FIT image? How does
dual-booting work? Does the user get a menu to choose a configuration
they want to boot if multiple entries are compatible with the detected
board?

Upstream U-Boot exports some variables (such as $soc and $board) to the
shell environment so that scripts can use them. What I usually end up
doing is put files (zImage, DTB, ...) in locations based on those names
so that I can boot all systems from the same SD card (or TFTP/NFS setup)
yet retain the possibility to update each of the files separately. Maybe
something like that could work for Chromebooks. If you locate files by
filename you become much less reliable on the content itself. Files
could be named tegra124-nyan-big.dtb even if the compatible was just
"google,big". The same goes for additional properties in FIT images.

Thierry

Olof Johansson Aug. 20, 2014, 3:40 p.m. UTC | #14

On Wed, Aug 20, 2014 at 7:32 AM, Thierry Reding
<[e-mail]> wrote:
> On Wed, Aug 20, 2014 at 06:29:14AM -0700, Olof Johansson wrote:
>> On Mon, Aug 18, 2014 at 4:43 PM, Stephen Warren <[e-mail]> wrote:
> [...]
>> > Again, this board *isn't* Nyan, so it should pretend that it is.
>>
>> It is a derivative design of the nyan reference platform, and it is
>> compatible with it. It is perfectly fine to claim to be compatible
>> with it. I'm sorry, but you're just wrong here.
>
> I guess that depends a little on how you define compatibility. I had
> always assumed that the top-level compatible string would be a sort of
> "checksum" over the rest of the content. Which, admittedly, makes it
> kind of redundant. Compatibility could mean a lot of things. Does it
> mean any kernel/DTB compatible with one device could run on any device
> derived from it? Does compatibility mean it needs to provide full
> functionality or is it still compatible if it runs at a reduced feature
> set but doesn't "break" otherwise?

Consider:
        compatible = "foo,x", "foo,y";

My interpretation is:  foo,x is compatible with foo,y if and only if:

foo,x can be driven by the same code as foo,y -- i.e. the driver
doesn't need changes for basic things to work (and nothing should be
broken).

foo,x _can_ be a superset though. It could have features that foo,y
doesn't have, that needs driver changes to take advantage of. But
using the foo,y driver with a foo,x device should give you the foo,y
functionality.

The simple case is where foo,x is more or less identical to foo,y, but
there might be some implementation-specific bugs that makes it useful
to be able to, at some point in the future, tell if you're running on
a foo,x or foo,y device even if the code is identical today.


In this particular case, google,nyan and google,nyan-big are very
similar. There are some differences in panels, etc, but it's described
in the individual device trees already, but things will come up and be
functional even if you boot with the wrong device tree (as far as I
know). Andrew has done that in the past, as far as I know.


-Olof

Andrew Bresticker Aug. 20, 2014, 5:25 p.m. UTC | #15

> It's been a long time since I've used FIT, but I seem to remember that
> it was simply a device tree-based description of a file format. As such
> couldn't you add an additional property to the configuration entry that
> the bootloader could match on? That would avoid the need to parse an
> embedded device tree and it might be useful to keep variants for the
> same board in the same FIT image.

Yes, I suppose something like that would be possible, however it's not
just depthcharge that matches to configurations based on the
compatible string within the configuration's FDT blob, this is the
convention U-Boot uses as well when booting FIT images.

> Perhaps you can explain a little more what the use-cases are. For
> example how are people suppose to run an upstream kernel on one of these
> Chromebooks?

There are a few ways you could run an upstream kernel:

1) Building your own verified-boot-wrapped FIT image and replacing the
existing one using tools found in the ChromiumOS tree [0].  This is
the workflow must of our developers use when working on product
kernels, but could just as easily be done with an upstream kernel.

2) Using U-Boot, either through the built-in legacy mode payload
(Ctrl-L at the developer screen) or by replacing the vboot-wrapped FIT
image with one that has U-Boot as a payload rather than a kernel [1].

3) If you're willing to flash your own firmware to the device, you can
build netboot-enabled firmware form the ChromiumOS tree that will load
a FIT image over the network.  This is the most flexible, as it
doesn't require the root device to be partitioned in any particular
way and allows you to boot non-ChromeOS distributions (e.g. Ubuntu).
This is what Dylan and I usually do when working on upstream kernels.

> How does dual-booting work?

You could dual-boot with the legacy-mode U-Boot, described above.

> Does the user get a menu to choose a configuration they want to boot if
> multiple entries are compatible with the detected board?

IIRC depthcharge will just pick the first one if there are multiple
exact matches.

[0] http://www.chromium.org/chromium-os/how-tos-and-troubleshooting/kernel-faq#TOC-How-to-quickly-test-kernel-modifications-the-fast-way-
[1] http://www.chromium.org/chromium-os/u-boot-porting-guide/using-nv-u-boot-on-the-samsung-arm-chromebook#TOC-Installing-nv-U-Boot-chained-U-Boot-method-

Thierry Reding Aug. 21, 2014, 7:19 a.m. UTC | #16

On Wed, Aug 20, 2014 at 08:40:33AM -0700, Olof Johansson wrote:
> On Wed, Aug 20, 2014 at 7:32 AM, Thierry Reding
> <[e-mail]> wrote:
> > On Wed, Aug 20, 2014 at 06:29:14AM -0700, Olof Johansson wrote:
> >> On Mon, Aug 18, 2014 at 4:43 PM, Stephen Warren <[e-mail]> wrote:
> > [...]
> >> > Again, this board *isn't* Nyan, so it should pretend that it is.
> >>
> >> It is a derivative design of the nyan reference platform, and it is
> >> compatible with it. It is perfectly fine to claim to be compatible
> >> with it. I'm sorry, but you're just wrong here.
> >
> > I guess that depends a little on how you define compatibility. I had
> > always assumed that the top-level compatible string would be a sort of
> > "checksum" over the rest of the content. Which, admittedly, makes it
> > kind of redundant. Compatibility could mean a lot of things. Does it
> > mean any kernel/DTB compatible with one device could run on any device
> > derived from it? Does compatibility mean it needs to provide full
> > functionality or is it still compatible if it runs at a reduced feature
> > set but doesn't "break" otherwise?
> 
> Consider:
>         compatible = "foo,x", "foo,y";
> 
> My interpretation is:  foo,x is compatible with foo,y if and only if:
> 
> foo,x can be driven by the same code as foo,y -- i.e. the driver
> doesn't need changes for basic things to work (and nothing should be
> broken).
> 
> foo,x _can_ be a superset though. It could have features that foo,y
> doesn't have, that needs driver changes to take advantage of. But
> using the foo,y driver with a foo,x device should give you the foo,y
> functionality.
> 
> The simple case is where foo,x is more or less identical to foo,y, but
> there might be some implementation-specific bugs that makes it useful
> to be able to, at some point in the future, tell if you're running on
> a foo,x or foo,y device even if the code is identical today.
> 
> 
> In this particular case, google,nyan and google,nyan-big are very
> similar. There are some differences in panels, etc, but it's described
> in the individual device trees already, but things will come up and be
> functional even if you boot with the wrong device tree (as far as I
> know). Andrew has done that in the past, as far as I know.

The problem with the above that it makes a bunch of assumptions about
drivers. It's perfectly possible for one OS to be implemented in a way
that matches your expectations above, while another OS would not work
the same way.

In particular since you point out panels being different: you typically
can't rely on a driver for one panel to support another panel as well.
While it's true that many panels provide an EDID for the display timings
it's equally well possible that some panels don't, therefore a driver
for one panel can't drive another (because the timings are wrong). There
are other things that can be incompatible between panels such as power
up/down sequences and power supplies. All those together mean that the
panels aren't compatible and I'd argue that the panel is one of the key
features of a Chromebook. Booting a "google,nyan" DTB on a
"google,nyan-big" device may (depending on OS) in fact break
functionality and hence be incompatible.

Thierry

Stephen Warren Sept. 4, 2014, 7:40 p.m. UTC | #17

On 08/13/2014 01:14 PM, Dylan Reid wrote:
> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
> processor and is similar to the Venice2 reference platform.
>
> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
> and work on the 1266x768 models.  The HD models haven't yet been
> tested.
>
> WiFi does not work yet, it needs at least some PMIC changes to enable
> the 32k clock.
>
> The elan trackpad is not yet functional but hopefully will be soon as
> there are patches under review.
>
> There is also an issue on reboot because the TPM isn't reset.  It will
> cause the stock firmware to enter recovery mode.  This can be worked
> around by an EC-reset, press the refresh and power keys at the same
> time.

BTW, I'm only waiting on a few minor fixes for issues pointed out by 
Andreas before applying this patch:
* Resolution typo in the commit message.
* Sort order of the Makefile addition.
* pwm: label move.
* Stray content/syntax error in regulator@1 node.

I'm assuming you'll repost for that? I guess I could fix them up when 
applying, but I usually wouldn't.

Dylan Reid Sept. 4, 2014, 8:33 p.m. UTC | #18

On Thu, Sep 4, 2014 at 12:40 PM, Stephen Warren <[e-mail]> wrote:
> On 08/13/2014 01:14 PM, Dylan Reid wrote:
>>
>> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
>> processor and is similar to the Venice2 reference platform.
>>
>> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
>> and work on the 1266x768 models.  The HD models haven't yet been
>> tested.
>>
>> WiFi does not work yet, it needs at least some PMIC changes to enable
>> the 32k clock.
>>
>> The elan trackpad is not yet functional but hopefully will be soon as
>> there are patches under review.
>>
>> There is also an issue on reboot because the TPM isn't reset.  It will
>> cause the stock firmware to enter recovery mode.  This can be worked
>> around by an EC-reset, press the refresh and power keys at the same
>> time.
>
>
> BTW, I'm only waiting on a few minor fixes for issues pointed out by Andreas
> before applying this patch:

Thanks Stephen,

Sorry I've been MIA, things have been a little crazy here.

> * Resolution typo in the commit message.
> * Sort order of the Makefile addition.
> * pwm: label move.

If I move the pwm label, should I move the others as well?  Do we want
to use the same method that has been used for exynos5250?  Exynos has
a label on most things that are overridden and the .dts files that
override them, like exynos5250-snow.dts, access them with &label
syntax.  It's easy for me to do, but it will involve converting
venice2 and jetson as well to avoid label re-defines.

> * Stray content/syntax error in regulator@1 node.
>
> I'm assuming you'll repost for that? I guess I could fix them up when
> applying, but I usually wouldn't.

Stephen Warren Sept. 4, 2014, 9:04 p.m. UTC | #19

On 09/04/2014 02:33 PM, Dylan Reid wrote:
> On Thu, Sep 4, 2014 at 12:40 PM, Stephen Warren <[e-mail]> wrote:
>> On 08/13/2014 01:14 PM, Dylan Reid wrote:
>>>
>>> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
>>> processor and is similar to the Venice2 reference platform.
>>>
>>> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
>>> and work on the 1266x768 models.  The HD models haven't yet been
>>> tested.
>>>
>>> WiFi does not work yet, it needs at least some PMIC changes to enable
>>> the 32k clock.
>>>
>>> The elan trackpad is not yet functional but hopefully will be soon as
>>> there are patches under review.
>>>
>>> There is also an issue on reboot because the TPM isn't reset.  It will
>>> cause the stock firmware to enter recovery mode.  This can be worked
>>> around by an EC-reset, press the refresh and power keys at the same
>>> time.
>>
>>
>> BTW, I'm only waiting on a few minor fixes for issues pointed out by Andreas
>> before applying this patch:
>
> Thanks Stephen,
>
> Sorry I've been MIA, things have been a little crazy here.
>
>> * Resolution typo in the commit message.
>> * Sort order of the Makefile addition.
>> * pwm: label move.
>
> If I move the pwm label, should I move the others as well?  Do we want
> to use the same method that has been used for exynos5250?  Exynos has
> a label on most things that are overridden and the .dts files that
> override them, like exynos5250-snow.dts, access them with &label
> syntax.  It's easy for me to do, but it will involve converting
> venice2 and jetson as well to avoid label re-defines.

I think anything that's first defined in tegra124.dtsi should have the 
label defined in tegra124.dtsi, provided the label makes sens across all 
boards. From v2 of the patch, that looks like: dpaux, pwm. It looks like 
the pinmux label isn't used, so I'd suggest dropping that. The label 
name hdmi_ddc feels board-specific (since different boards could at 
least theoretically use different I2C controllers for DDC), so I'd leave 
that in the board dts file myself.

The &label { ... } syntax wouldn't be consistent with any of the other 
Tegra files at the moment, so I'd suggest sticking to the overall DT 
structure you already have in patch v2. I admit it's unfortunate that 
Exynos and Tegra use different node reference styles, but consistency 
between all the Tegra DT files feels most important to me right now:-)

Dylan Reid Sept. 4, 2014, 9:08 p.m. UTC | #20

On Thu, Sep 4, 2014 at 2:04 PM, Stephen Warren <[e-mail]> wrote:
> On 09/04/2014 02:33 PM, Dylan Reid wrote:
>>
>> On Thu, Sep 4, 2014 at 12:40 PM, Stephen Warren <[e-mail]>
>> wrote:
>>>
>>> On 08/13/2014 01:14 PM, Dylan Reid wrote:
>>>>
>>>>
>>>> The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
>>>> processor and is similar to the Venice2 reference platform.
>>>>
>>>> The keyboard, USB 2, audio, HDMI, sdcard, and emmc have been tested
>>>> and work on the 1266x768 models.  The HD models haven't yet been
>>>> tested.
>>>>
>>>> WiFi does not work yet, it needs at least some PMIC changes to enable
>>>> the 32k clock.
>>>>
>>>> The elan trackpad is not yet functional but hopefully will be soon as
>>>> there are patches under review.
>>>>
>>>> There is also an issue on reboot because the TPM isn't reset.  It will
>>>> cause the stock firmware to enter recovery mode.  This can be worked
>>>> around by an EC-reset, press the refresh and power keys at the same
>>>> time.
>>>
>>>
>>>
>>> BTW, I'm only waiting on a few minor fixes for issues pointed out by
>>> Andreas
>>> before applying this patch:
>>
>>
>> Thanks Stephen,
>>
>> Sorry I've been MIA, things have been a little crazy here.
>>
>>> * Resolution typo in the commit message.
>>> * Sort order of the Makefile addition.
>>> * pwm: label move.
>>
>>
>> If I move the pwm label, should I move the others as well?  Do we want
>> to use the same method that has been used for exynos5250?  Exynos has
>> a label on most things that are overridden and the .dts files that
>> override them, like exynos5250-snow.dts, access them with &label
>> syntax.  It's easy for me to do, but it will involve converting
>> venice2 and jetson as well to avoid label re-defines.
>
>
> I think anything that's first defined in tegra124.dtsi should have the label
> defined in tegra124.dtsi, provided the label makes sens across all boards.
> From v2 of the patch, that looks like: dpaux, pwm. It looks like the pinmux
> label isn't used, so I'd suggest dropping that. The label name hdmi_ddc
> feels board-specific (since different boards could at least theoretically
> use different I2C controllers for DDC), so I'd leave that in the board dts
> file myself.
>
> The &label { ... } syntax wouldn't be consistent with any of the other Tegra
> files at the moment, so I'd suggest sticking to the overall DT structure you
> already have in patch v2. I admit it's unfortunate that Exynos and Tegra use
> different node reference styles, but consistency between all the Tegra DT
> files feels most important to me right now:-)

Sounds good.  I'll do that, run a few tests and send the patches out by EOD.

Thanks,

Dylan

Patch

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index acb6b42..bebb4e7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -439,6 +439,7 @@  dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 	tegra114-dalmore.dtb \
 	tegra114-roth.dtb \
 	tegra114-tn7.dtb \
+	tegra124-nyan-big.dtb \
 	tegra124-jetson-tk1.dtb \
 	tegra124-venice2.dtb
 dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
new file mode 100644
index 0000000..79f1852
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -0,0 +1,1136 @@ 
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra124.dtsi"
+
+/ {
+	model = "Acer Chromebook 13";
+	compatible = "google,nyan-big", "nvidia,tegra124";
+
+	aliases {
+		rtc0 = "/i2c@0,7000d000/pmic@40";
+		rtc1 = "/rtc@0,7000e000";
+	};
+
+	memory {
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+
+	host1x@0,50000000 {
+		hdmi@0,54280000 {
+			status = "okay";
+
+			vdd-supply = <&vdd_3v3_hdmi>;
+			pll-supply = <&vdd_hdmi_pll>;
+			hdmi-supply = <&vdd_5v0_hdmi>;
+
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			nvidia,hpd-gpio =
+				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+		};
+
+		sor@0,54540000 {
+			status = "okay";
+
+			nvidia,dpaux = <&dpaux>;
+			nvidia,panel = <&panel>;
+		};
+
+		dpaux: dpaux@0,545c0000 {
+			vdd-supply = <&vdd_3v3_panel>;
+			status = "okay";
+		};
+	};
+
+	pinmux: pinmux@0,70000868 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinmux_default>;
+
+		pinmux_default: common {
+			dap_mclk1_pw4 {
+				nvidia,pins = "dap_mclk1_pw4";
+				nvidia,function = "extperiph1";
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			dap2_din_pa4 {
+				nvidia,pins = "dap2_din_pa4";
+				nvidia,function = "i2s1";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			dap2_dout_pa5 {
+				nvidia,pins = "dap2_dout_pa5",
+					      "dap2_fs_pa2",
+					      "dap2_sclk_pa3";
+				nvidia,function = "i2s1";
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			dvfs_pwm_px0 {
+				nvidia,pins = "dvfs_pwm_px0",
+					      "dvfs_clk_px2";
+				nvidia,function = "cldvfs";
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_clk_py0 {
+				nvidia,pins = "ulpi_clk_py0",
+					      "ulpi_nxt_py2",
+					      "ulpi_stp_py3";
+				nvidia,function = "spi1";
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_dir_py1 {
+				nvidia,pins = "ulpi_dir_py1";
+				nvidia,function = "spi1";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			cam_i2c_scl_pbb1 {
+				nvidia,pins = "cam_i2c_scl_pbb1",
+					      "cam_i2c_sda_pbb2";
+				nvidia,function = "i2c3";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			gen2_i2c_scl_pt5 {
+				nvidia,pins = "gen2_i2c_scl_pt5",
+					      "gen2_i2c_sda_pt6";
+				nvidia,function = "i2c2";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			pg4 {
+				nvidia,pins = "pg4",
+					      "pg5",
+					      "pg6",
+					      "pi3";
+				nvidia,function = "spi4";
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			pg7 {
+				nvidia,pins = "pg7";
+				nvidia,function = "spi4";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			ph1 {
+				nvidia,pins = "ph1";
+				nvidia,function = "pwm1";
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			pk0 {
+				nvidia,pins = "pk0",
+					      "kb_row15_ps7",
+					      "clk_32k_out_pa0";
+				nvidia,function = "soc";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_clk_pz0 {
+				nvidia,pins = "sdmmc1_clk_pz0";
+				nvidia,function = "sdmmc1";
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc1_cmd_pz1 {
+				nvidia,pins = "sdmmc1_cmd_pz1",
+					      "sdmmc1_dat0_py7",
+					      "sdmmc1_dat1_py6",
+					      "sdmmc1_dat2_py5",
+					      "sdmmc1_dat3_py4";
+				nvidia,function = "sdmmc1";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc3_clk_pa6 {
+				nvidia,pins = "sdmmc3_clk_pa6";
+				nvidia,function = "sdmmc3";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc3_cmd_pa7 {
+				nvidia,pins = "sdmmc3_cmd_pa7",
+					      "sdmmc3_dat0_pb7",
+					      "sdmmc3_dat1_pb6",
+					      "sdmmc3_dat2_pb5",
+					      "sdmmc3_dat3_pb4",
+					      "kb_col4_pq4",
+					      "sdmmc3_clk_lb_out_pee4",
+					      "sdmmc3_clk_lb_in_pee5",
+					      "sdmmc3_cd_n_pv2";
+				nvidia,function = "sdmmc3";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc4_clk_pcc4 {
+				nvidia,pins = "sdmmc4_clk_pcc4";
+				nvidia,function = "sdmmc4";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc4_cmd_pt7 {
+				nvidia,pins = "sdmmc4_cmd_pt7",
+					      "sdmmc4_dat0_paa0",
+					      "sdmmc4_dat1_paa1",
+					      "sdmmc4_dat2_paa2",
+					      "sdmmc4_dat3_paa3",
+					      "sdmmc4_dat4_paa4",
+					      "sdmmc4_dat5_paa5",
+					      "sdmmc4_dat6_paa6",
+					      "sdmmc4_dat7_paa7";
+				nvidia,function = "sdmmc4";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			pwr_i2c_scl_pz6 {
+				nvidia,pins = "pwr_i2c_scl_pz6",
+					      "pwr_i2c_sda_pz7";
+				nvidia,function = "i2cpwr";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			jtag_rtck {
+				nvidia,pins = "jtag_rtck";
+				nvidia,function = "rtck";
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			clk_32k_in {
+				nvidia,pins = "clk_32k_in";
+				nvidia,function = "clk";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			core_pwr_req {
+				nvidia,pins = "core_pwr_req";
+				nvidia,function = "pwron";
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			cpu_pwr_req {
+				nvidia,pins = "cpu_pwr_req";
+				nvidia,function = "cpu";
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			pwr_int_n {
+				nvidia,pins = "pwr_int_n";
+				nvidia,function = "pmi";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			reset_out_n {
+				nvidia,pins = "reset_out_n";
+				nvidia,function = "reset_out_n";
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			clk3_out_pee0 {
+				nvidia,pins = "clk3_out_pee0";
+				nvidia,function = "extperiph3";
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			gen1_i2c_sda_pc5 {
+				nvidia,pins = "gen1_i2c_sda_pc5",
+					      "gen1_i2c_scl_pc4";
+				nvidia,function = "i2c1";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			hdmi_cec_pee3 {
+				nvidia,pins = "hdmi_cec_pee3";
+				nvidia,function = "cec";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+			hdmi_int_pn7 {
+				nvidia,pins = "hdmi_int_pn7";
+				nvidia,function = "rsvd1";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			ddc_scl_pv4 {
+				nvidia,pins = "ddc_scl_pv4",
+					      "ddc_sda_pv5";
+				nvidia,function = "i2c4";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
+			};
+			kb_row10_ps2 {
+				nvidia,pins = "kb_row10_ps2";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_row9_ps1 {
+				nvidia,pins = "kb_row9_ps1";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			usb_vbus_en0_pn4 {
+				nvidia,pins = "usb_vbus_en0_pn4",
+					      "usb_vbus_en1_pn5";
+				nvidia,function = "usb";
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			drive_sdio1 {
+				nvidia,pins = "drive_sdio1";
+				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+				nvidia,pull-down-strength = <36>;
+				nvidia,pull-up-strength = <20>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
+			};
+			drive_sdio3 {
+				nvidia,pins = "drive_sdio3";
+				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+				nvidia,pull-down-strength = <22>;
+				nvidia,pull-up-strength = <36>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+			};
+			drive_gma {
+				nvidia,pins = "drive_gma";
+				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+				nvidia,pull-down-strength = <2>;
+				nvidia,pull-up-strength = <1>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+				nvidia,drive-type = <1>;
+			};
+			codec_irq_l {
+				nvidia,pins = "ph4";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			lcd_bl_en {
+				nvidia,pins = "ph2";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			touch_irq_l {
+				nvidia,pins = "gpio_w3_aud_pw3";
+				nvidia,function = "spi6";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			tpm_davint_l {
+				nvidia,pins = "ph6";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ts_irq_l {
+				nvidia,pins = "pk2";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ts_reset_l {
+				nvidia,pins = "pk4";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ts_shdn_l {
+				nvidia,pins = "pk1";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ph7 {
+				nvidia,pins = "ph7";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_col0_ap {
+				nvidia,pins = "kb_col0_pq0";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			lid_open {
+				nvidia,pins = "kb_row4_pr4";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			en_vdd_sd {
+				nvidia,pins = "kb_row0_pr0";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ac_ok {
+				nvidia,pins = "pj0";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sensor_irq_l {
+				nvidia,pins = "pi6";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			wifi_en {
+				nvidia,pins = "gpio_x7_aud_px7";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			en_vdd_bl {
+				nvidia,pins = "dap3_dout_pp2";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			en_vdd_hdmi {
+				nvidia,pins = "spdif_in_pk6";
+				nvidia,function = "spdif";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			soc_warm_reset_l {
+				nvidia,pins = "pi5";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			hp_det_l {
+				nvidia,pins = "pi7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			mic_det_l {
+				nvidia,pins = "kb_row7_pr7";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+		};
+	};
+
+	serial@0,70006000 {
+		/* Debug connector on the bottom of the board near SD card. */
+		status = "okay";
+	};
+
+	pwm: pwm@0,7000a000 {
+		status = "okay";
+	};
+
+	i2c@0,7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+
+		acodec: audio-codec@10 {
+			compatible = "maxim,max98090";
+			reg = <0x10>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+		};
+
+		temperature-sensor@4c {
+			compatible = "ti,tmp451";
+			reg = <0x4c>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
+
+			#thermal-sensor-cells = <1>;
+		};
+	};
+
+	i2c@0,7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@0,7000c500 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		tpm@20 {
+			compatible = "infineon,slb9645tt";
+			reg = <0x20>;
+		};
+	};
+
+	hdmi_ddc: i2c@0,7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@0,7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		pmic: pmic@40 {
+			compatible = "ams,as3722";
+			reg = <0x40>;
+			interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+			ams,system-power-controller;
+
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&as3722_default>;
+
+			as3722_default: pinmux {
+				gpio0 {
+					pins = "gpio0";
+					function = "gpio";
+					bias-pull-down;
+				};
+
+				gpio1 {
+					pins = "gpio1";
+					function = "gpio";
+					bias-pull-up;
+				};
+
+				gpio2_4_7 {
+					pins = "gpio2", "gpio4", "gpio7";
+					function = "gpio";
+					bias-pull-up;
+				};
+
+				gpio3_6 {
+					pins = "gpio3", "gpio6";
+					bias-high-impedance;
+				};
+
+				gpio5 {
+					pins = "gpio5";
+					function = "clk32k-out";
+					bias-pull-down;
+				};
+			};
+
+			regulators {
+				vsup-sd2-supply = <&vdd_5v0_sys>;
+				vsup-sd3-supply = <&vdd_5v0_sys>;
+				vsup-sd4-supply = <&vdd_5v0_sys>;
+				vsup-sd5-supply = <&vdd_5v0_sys>;
+				vin-ldo0-supply = <&vdd_1v35_lp0>;
+				vin-ldo1-6-supply = <&vdd_3v3_run>;
+				vin-ldo2-5-7-supply = <&vddio_1v8>;
+				vin-ldo3-4-supply = <&vdd_3v3_sys>;
+				vin-ldo9-10-supply = <&vdd_5v0_sys>;
+				vin-ldo11-supply = <&vdd_3v3_run>;
+
+				sd0 {
+					regulator-name = "+VDD_CPU_AP";
+					regulator-min-microvolt = <700000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-min-microamp = <3500000>;
+					regulator-max-microamp = <3500000>;
+					regulator-always-on;
+					regulator-boot-on;
+					ams,ext-control = <2>;
+				};
+
+				sd1 {
+					regulator-name = "+VDD_CORE";
+					regulator-min-microvolt = <700000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-min-microamp = <2500000>;
+					regulator-max-microamp = <4000000>;
+					regulator-always-on;
+					regulator-boot-on;
+					ams,ext-control = <1>;
+				};
+
+				vdd_1v35_lp0: sd2 {
+					regulator-name = "+1.35V_LP0(sd2)";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				sd3 {
+					regulator-name = "+1.35V_LP0(sd3)";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				vdd_1v05_run: sd4 {
+					regulator-name = "+1.05V_RUN";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+				};
+
+				vddio_1v8: sd5 {
+					regulator-name = "+1.8V_VDDIO";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				sd6 {
+					regulator-name = "+VDD_GPU_AP";
+					regulator-min-microvolt = <650000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-min-microamp = <3500000>;
+					regulator-max-microamp = <3500000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo0 {
+					regulator-name = "+1.05V_RUN_AVDD";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+					regulator-boot-on;
+					regulator-always-on;
+					ams,ext-control = <1>;
+				};
+
+				ldo1 {
+					regulator-name = "+1.8V_RUN_CAM";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo2 {
+					regulator-name = "+1.2V_GEN_AVDD";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo3 {
+					regulator-name = "+1.00V_LP0_VDD_RTC";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-boot-on;
+					regulator-always-on;
+					ams,enable-tracking;
+				};
+
+				vdd_run_cam: ldo4 {
+					regulator-name = "+3.3V_RUN_CAM";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				ldo5 {
+					regulator-name = "+1.2V_RUN_CAM_FRONT";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				vddio_sdmmc3: ldo6 {
+					regulator-name = "+VDDIO_SDMMC3";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				ldo7 {
+					regulator-name = "+1.05V_RUN_CAM_REAR";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+				};
+
+				ldo9 {
+					regulator-name = "+2.8V_RUN_TOUCH";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				ldo10 {
+					regulator-name = "+2.8V_RUN_CAM_AF";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				ldo11 {
+					regulator-name = "+1.8V_RUN_VPP_FUSE";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+			};
+		};
+	};
+
+	spi@0,7000d400 {
+		status = "okay";
+
+		cros_ec: cros-ec@0 {
+			compatible = "google,cros-ec-spi";
+			spi-max-frequency = <3000000>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+			reg = <0>;
+
+			google,cros-ec-spi-msg-delay = <2000>;
+
+			i2c-tunnel {
+				compatible = "google,cros-ec-i2c-tunnel";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				google,remote-bus = <0>;
+
+				charger: bq24735@9 {
+					compatible = "ti,bq24735";
+					reg = <0x9>;
+					interrupt-parent = <&gpio>;
+					interrupts = <TEGRA_GPIO(J, 0)
+							GPIO_ACTIVE_HIGH>;
+					ti,ac-detect-gpios = <&gpio
+							TEGRA_GPIO(J, 0)
+							GPIO_ACTIVE_HIGH>;
+				};
+
+				battery: sbs-battery@b {
+					compatible = "sbs,sbs-battery";
+					reg = <0xb>;
+					sbs,i2c-retry-count = <2>;
+					sbs,poll-retry-count = <10>;
+					power-supplies = <&charger>;
+				};
+			};
+		};
+	};
+
+	spi@0,7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+
+		flash@0 {
+			compatible = "winbond,w25q32dw";
+			reg = <0>;
+		};
+	};
+
+	pmc@0,7000e400 {
+		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <0>;
+		nvidia,cpu-pwr-good-time = <500>;
+		nvidia,cpu-pwr-off-time = <300>;
+		nvidia,core-pwr-good-time = <641 3845>;
+		nvidia,core-pwr-off-time = <61036>;
+		nvidia,core-power-req-active-high;
+		nvidia,sys-clock-req-active-high;
+	};
+
+	hda@0,70030000 {
+		status = "okay";
+	};
+
+	sdhci@0,700b0000 { /* WiFi/BT on this bus */
+		status = "okay";
+		power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
+		bus-width = <4>;
+		no-1-8-v;
+		non-removable;
+	};
+
+	sdhci@0,700b0400 { /* SD Card on this bus */
+		status = "okay";
+		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+		power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+		wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+		bus-width = <4>;
+		no-1-8-v;
+		vqmmc-supply = <&vddio_sdmmc3>;
+	};
+
+	sdhci@0,700b0600 { /* eMMC on this bus */
+		status = "okay";
+		bus-width = <8>;
+		no-1-8-v;
+		non-removable;
+	};
+
+	ahub@0,70300000 {
+		i2s@0,70301100 {
+			status = "okay";
+		};
+	};
+
+	usb@0,7d000000 { /* Rear external USB port. */
+		status = "okay";
+	};
+
+	usb-phy@0,7d000000 {
+		status = "okay";
+		vbus-supply = <&vdd_usb1_vbus>;
+	};
+
+	usb@0,7d004000 { /* Internal webcam. */
+		status = "okay";
+	};
+
+	usb-phy@0,7d004000 {
+		status = "okay";
+		vbus-supply = <&vdd_run_cam>;
+	};
+
+	usb@0,7d008000 { /* Left external USB port. */
+		status = "okay";
+	};
+
+	usb-phy@0,7d008000 {
+		status = "okay";
+		vbus-supply = <&vdd_usb3_vbus>;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+
+		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+		power-supply = <&vdd_led>;
+		pwms = <&pwm 1 1000000>;
+
+		default-brightness-level = <224>;
+		brightness-levels =
+			<  0   1   2   3   4   5   6   7
+			   8   9  10  11  12  13  14  15
+			  16  17  18  19  20  21  22  23
+			  24  25  26  27  28  29  30  31
+			  32  33  34  35  36  37  38  39
+			  40  41  42  43  44  45  46  47
+			  48  49  50  51  52  53  54  55
+			  56  57  58  59  60  61  62  63
+			  64  65  66  67  68  69  70  71
+			  72  73  74  75  76  77  78  79
+			  80  81  82  83  84  85  86  87
+			  88  89  90  91  92  93  94  95
+			  96  97  98  99 100 101 102 103
+			 104 105 106 107 108 109 110 111
+			 112 113 114 115 116 117 118 119
+			 120 121 122 123 124 125 126 127
+			 128 129 130 131 132 133 134 135
+			 136 137 138 139 140 141 142 143
+			 144 145 146 147 148 149 150 151
+			 152 153 154 155 156 157 158 159
+			 160 161 162 163 164 165 166 167
+			 168 169 170 171 172 173 174 175
+			 176 177 178 179 180 181 182 183
+			 184 185 186 187 188 189 190 191
+			 192 193 194 195 196 197 198 199
+			 200 201 202 203 204 205 206 207
+			 208 209 210 211 212 213 214 215
+			 216 217 218 219 220 221 222 223
+			 224 225 226 227 228 229 230 231
+			 232 233 234 235 236 237 238 239
+			 240 241 242 243 244 245 246 247
+			 248 249 250 251 252 253 254 255
+			 256>;
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clk32k_in: clock@0 {
+			compatible = "fixed-clock";
+			reg = <0>;
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		lid {
+			label = "Lid";
+			gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
+			linux,input-type = <5>;
+			linux,code = <KEY_RESERVED>;
+			debounce-interval = <1>;
+			gpio-key,wakeup;
+		};
+
+		power {
+			label = "Power";
+			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			debounce-interval = <30>;
+			gpio-key,wakeup;
+		};
+	};
+
+	panel: panel {
+		compatible = "auo,b133xtn01";
+
+		backlight = <&backlight>;
+		ddc-i2c-bus = <&dpaux>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_mux: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "+VDD_MUX";
+			regulator-min-microvolt = <12000000>;
+			regulator-max-microvolt = <12000000>;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+
+		vdd_5v0_sys: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "+5V_SYS";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+			regulator-boot-on;
+			vin-supply = <&vdd_mux>;
+		};
+
+		vdd_3v3_sys: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "+3.3V_SYS";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			vin-supply = <&vdd_mux>;
+		};
+
+		vdd_3v3_run: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "+3.3V_RUN";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_3v3_sys>;
+		};
+
+		vdd_3v3_hdmi: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			vin-supply = <&vdd_3v3_run>;
+		};
+
+		vdd_led: regulator@5 {
+			compatible = "regulator-fixed";
+			reg = <5>;
+			regulator-name = "+VDD_LED";
+			gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_mux>;
+		};
+
+		vdd_5v0_ts: regulator@6 {
+			compatible = "regulator-fixed";
+			reg = <6>;
+			regulator-name = "+5V_VDD_TS_SW";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-boot-on;
+			gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_5v0_sys>;
+		};
+
+		vdd_usb1_vbus: regulator@7 {
+			compatible = "regulator-fixed";
+			reg = <7>;
+			regulator-name = "+5V_USB_HS";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			gpio-open-drain;
+			vin-supply = <&vdd_5v0_sys>;
+		};
+
+		vdd_usb3_vbus: regulator@8 {
+			compatible = "regulator-fixed";
+			reg = <8>;
+			regulator-name = "+5V_USB_SS";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			gpio-open-drain;
+			vin-supply = <&vdd_5v0_sys>;
+		};
+
+		vdd_3v3_panel: regulator@9 {
+			compatible = "regulator-fixed";
+			reg = <9>;
+			regulator-name = "+3.3V_PANEL";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_3v3_run>;
+		};
+
+		vdd_3v3_lp0: regulator@10 {
+			compatible = "regulator-fixed";
+			reg = <10>;
+			regulator-name = "+3.3V_LP0";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			/*
+			 * TODO: find a way to wire this up with the USB EHCI
+			 * controllers so that it can be enabled on demand.
+			 */
+			regulator-always-on;
+			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_3v3_sys>;
+		};
+
+		vdd_hdmi_pll: regulator@11 {
+			compatible = "regulator-fixed";
+			reg = <11>;
+			regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+			regulator-min-microvolt = <1050000>;
+			regulator-max-microvolt = <1050000>;
+			gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+			vin-supply = <&vdd_1v05_run>;
+		};
+
+		vdd_5v0_hdmi: regulator@12 {
+			compatible = "regulator-fixed";
+			reg = <12>;
+			regulator-name = "+5V_HDMI_CON";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_5v0_sys>;
+		};
+	};
+
+	sound {
+		compatible = "nvidia,tegra-audio-max98090-nyan-big",
+			     "nvidia,tegra-audio-max98090";
+		nvidia,model = "Acer Chromebook 13";
+
+		nvidia,audio-routing =
+			"Headphones", "HPR",
+			"Headphones", "HPL",
+			"Speakers", "SPKR",
+			"Speakers", "SPKL",
+			"Mic Jack", "MICBIAS",
+			"DMICL", "Int Mic",
+			"DMICR", "Int Mic",
+			"IN34", "Mic Jack";
+
+		nvidia,i2s-controller = <&tegra_i2s1>;
+		nvidia,audio-codec = <&acodec>;
+
+		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA124_CLK_EXTERN1>;
+		clock-names = "pll_a", "pll_a_out0", "mclk";
+
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
+	};
+};
+
+#include "cros-ec-keyboard.dtsi"