| Message ID | 1412175188-28278-5-git-send-email-boris.brezillon@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Oct 01, 2014 at 04:53:01PM +0200, Boris Brezillon wrote: > From: Boris BREZILLON <boris.brezillon@free-electrons.com> > > The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12, > at91sam9x5 family or sama5d3 family) provide a PWM device. > > The DT bindings used for this PWM device is following the default 3 cells > bindings described in Documentation/devicetree/bindings/pwm/pwm.txt. > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > --- > .../devicetree/bindings/pwm/atmel-hlcdc-pwm.txt | 55 ++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > new file mode 100644 > index 0000000..86ad3e2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > @@ -0,0 +1,55 @@ > +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) PWM driver > + > +The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. > +See ../mfd/atmel-hlcdc.txt for more details. > + > +Required properties: > + - compatible: value should be one of the following: > + "atmel,hlcdc-pwm" > + - pinctr-names: the pin control state names. Should contain "default". > + - pinctrl-0: should contain the pinctrl states described by pinctrl > + default. > + - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells > + bindings defined in Documentation/devicetree/bindings/pwm/pwm.txt. > + The first cell encodes the PWM id (0 is the only acceptable value here, > + because the chip only provide one PWM). > + The second cell encodes the PWM period in nanoseconds. > + The third cell encodes the PWM flags (the only supported flag is > + PWM_POLARITY_INVERTED) Given that this already refers to the default 3 cells binding it doesn't need to repeat part of the contents of pwm.txt. With that fixed and assuming you'd like this to be merged via the same tree that the DRM and or MFD driver is, this patch: Acked-by: Thierry Reding <thierry.reding@gmail.com> If you'd prefer this to go through the PWM tree just let me know. Thierry
On Mon, Oct 06, 2014 at 11:13:51AM +0100, Thierry Reding wrote: > On Wed, Oct 01, 2014 at 04:53:01PM +0200, Boris Brezillon wrote: > > From: Boris BREZILLON <boris.brezillon@free-electrons.com> > > > > The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12, > > at91sam9x5 family or sama5d3 family) provide a PWM device. > > > > The DT bindings used for this PWM device is following the default 3 cells > > bindings described in Documentation/devicetree/bindings/pwm/pwm.txt. > > > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > > --- > > .../devicetree/bindings/pwm/atmel-hlcdc-pwm.txt | 55 ++++++++++++++++++++++ > > 1 file changed, 55 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > > > diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > new file mode 100644 > > index 0000000..86ad3e2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > @@ -0,0 +1,55 @@ > > +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) PWM driver > > + > > +The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. > > +See ../mfd/atmel-hlcdc.txt for more details. > > + > > +Required properties: > > + - compatible: value should be one of the following: > > + "atmel,hlcdc-pwm" > > + - pinctr-names: the pin control state names. Should contain "default". > > + - pinctrl-0: should contain the pinctrl states described by pinctrl > > + default. > > + - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells > > + bindings defined in Documentation/devicetree/bindings/pwm/pwm.txt. > > + The first cell encodes the PWM id (0 is the only acceptable value here, > > + because the chip only provide one PWM). > > + The second cell encodes the PWM period in nanoseconds. > > + The third cell encodes the PWM flags (the only supported flag is > > + PWM_POLARITY_INVERTED) > > Given that this already refers to the default 3 cells binding it doesn't > need to repeat part of the contents of pwm.txt. Given that pwm.txt states: pwm-specifier : array of #pwm-cells specifying the given PWM (controller specific) I'd leave it here. Just because pwm.txt gives an example of a controller specific meaning for the pwm cells, I don't think we should rely on it everywhere. Mark.
On Mon, Oct 06, 2014 at 12:33:26PM +0100, Mark Rutland wrote: > On Mon, Oct 06, 2014 at 11:13:51AM +0100, Thierry Reding wrote: > > On Wed, Oct 01, 2014 at 04:53:01PM +0200, Boris Brezillon wrote: > > > From: Boris BREZILLON <boris.brezillon@free-electrons.com> > > > > > > The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12, > > > at91sam9x5 family or sama5d3 family) provide a PWM device. > > > > > > The DT bindings used for this PWM device is following the default 3 cells > > > bindings described in Documentation/devicetree/bindings/pwm/pwm.txt. > > > > > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > > > --- > > > .../devicetree/bindings/pwm/atmel-hlcdc-pwm.txt | 55 ++++++++++++++++++++++ > > > 1 file changed, 55 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > > > > > diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > > new file mode 100644 > > > index 0000000..86ad3e2 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > > @@ -0,0 +1,55 @@ > > > +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) PWM driver > > > + > > > +The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. > > > +See ../mfd/atmel-hlcdc.txt for more details. > > > + > > > +Required properties: > > > + - compatible: value should be one of the following: > > > + "atmel,hlcdc-pwm" > > > + - pinctr-names: the pin control state names. Should contain "default". > > > + - pinctrl-0: should contain the pinctrl states described by pinctrl > > > + default. > > > + - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells > > > + bindings defined in Documentation/devicetree/bindings/pwm/pwm.txt. > > > + The first cell encodes the PWM id (0 is the only acceptable value here, > > > + because the chip only provide one PWM). > > > + The second cell encodes the PWM period in nanoseconds. > > > + The third cell encodes the PWM flags (the only supported flag is > > > + PWM_POLARITY_INVERTED) > > > > Given that this already refers to the default 3 cells binding it doesn't > > need to repeat part of the contents of pwm.txt. > > Given that pwm.txt states: > > pwm-specifier : array of #pwm-cells specifying the given PWM > (controller specific) It also goes on to say that: " pwm-specifier typically encodes the chip-relative PWM number and the PWM period in nanoseconds. Optionally, the pwm-specifier can encode a number of flags (defined in <dt-bindings/pwm/pwm.h>) in a third cell: - PWM_POLARITY_INVERTED: invert the PWM signal polarity " > I'd leave it here. Just because pwm.txt gives an example of a controller > specific meaning for the pwm cells, I don't think we should rely on it > everywhere. If we do have a default meaning for a specifier and the majority (in case of PWM every single one) of the device-specific bindings use it, then I don't think it makes sense to duplicate information everywhere else. We've been doing the same thing across the kernel for a long time now, why should PWM be special? Thierry
On Mon, 6 Oct 2014 12:13:51 +0200 Thierry Reding <thierry.reding@gmail.com> wrote: > On Wed, Oct 01, 2014 at 04:53:01PM +0200, Boris Brezillon wrote: > > From: Boris BREZILLON <boris.brezillon@free-electrons.com> > > > > The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12, > > at91sam9x5 family or sama5d3 family) provide a PWM device. > > > > The DT bindings used for this PWM device is following the default 3 cells > > bindings described in Documentation/devicetree/bindings/pwm/pwm.txt. > > > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > > --- > > .../devicetree/bindings/pwm/atmel-hlcdc-pwm.txt | 55 ++++++++++++++++++++++ > > 1 file changed, 55 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > > > diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > new file mode 100644 > > index 0000000..86ad3e2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > @@ -0,0 +1,55 @@ > > +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) PWM driver > > + > > +The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. > > +See ../mfd/atmel-hlcdc.txt for more details. > > + > > +Required properties: > > + - compatible: value should be one of the following: > > + "atmel,hlcdc-pwm" > > + - pinctr-names: the pin control state names. Should contain "default". > > + - pinctrl-0: should contain the pinctrl states described by pinctrl > > + default. > > + - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells > > + bindings defined in Documentation/devicetree/bindings/pwm/pwm.txt. > > + The first cell encodes the PWM id (0 is the only acceptable value here, > > + because the chip only provide one PWM). > > + The second cell encodes the PWM period in nanoseconds. > > + The third cell encodes the PWM flags (the only supported flag is > > + PWM_POLARITY_INVERTED) > > Given that this already refers to the default 3 cells binding it doesn't > need to repeat part of the contents of pwm.txt. > > With that fixed and assuming you'd like this to be merged via the same > tree that the DRM and or MFD driver is, this patch: > > Acked-by: Thierry Reding <thierry.reding@gmail.com> > > If you'd prefer this to go through the PWM tree just let me know. Yes I'd prefer this solution, but shouldn't we wait for Lee to take the first two patches in his tree ?
On Mon, Oct 06, 2014 at 02:59:12PM +0200, Boris Brezillon wrote: > On Mon, 6 Oct 2014 12:13:51 +0200 > Thierry Reding <thierry.reding@gmail.com> wrote: > > > On Wed, Oct 01, 2014 at 04:53:01PM +0200, Boris Brezillon wrote: > > > From: Boris BREZILLON <boris.brezillon@free-electrons.com> > > > > > > The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12, > > > at91sam9x5 family or sama5d3 family) provide a PWM device. > > > > > > The DT bindings used for this PWM device is following the default 3 cells > > > bindings described in Documentation/devicetree/bindings/pwm/pwm.txt. > > > > > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > > > --- > > > .../devicetree/bindings/pwm/atmel-hlcdc-pwm.txt | 55 ++++++++++++++++++++++ > > > 1 file changed, 55 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > > > > > diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > > new file mode 100644 > > > index 0000000..86ad3e2 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > > @@ -0,0 +1,55 @@ > > > +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) PWM driver > > > + > > > +The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. > > > +See ../mfd/atmel-hlcdc.txt for more details. > > > + > > > +Required properties: > > > + - compatible: value should be one of the following: > > > + "atmel,hlcdc-pwm" > > > + - pinctr-names: the pin control state names. Should contain "default". > > > + - pinctrl-0: should contain the pinctrl states described by pinctrl > > > + default. > > > + - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells > > > + bindings defined in Documentation/devicetree/bindings/pwm/pwm.txt. > > > + The first cell encodes the PWM id (0 is the only acceptable value here, > > > + because the chip only provide one PWM). > > > + The second cell encodes the PWM period in nanoseconds. > > > + The third cell encodes the PWM flags (the only supported flag is > > > + PWM_POLARITY_INVERTED) > > > > Given that this already refers to the default 3 cells binding it doesn't > > need to repeat part of the contents of pwm.txt. > > > > With that fixed and assuming you'd like this to be merged via the same > > tree that the DRM and or MFD driver is, this patch: > > > > Acked-by: Thierry Reding <thierry.reding@gmail.com> > > > > If you'd prefer this to go through the PWM tree just let me know. > > Yes I'd prefer this solution, but shouldn't we wait for Lee to take the > first two patches in his tree ? Yes we should. Dependencies could get a little messy to deal with. Perhaps if it isn't too late yet, Lee could take this into the MFD tree for 3.18 and then we can take the PWM and DRM patches for 3.19. Another possibility would be to take the MFD patches into a tree and provide a stable branch for David and me to pull into our trees. Thierry
diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt new file mode 100644 index 0000000..86ad3e2 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt @@ -0,0 +1,55 @@ +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) PWM driver + +The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. +See ../mfd/atmel-hlcdc.txt for more details. + +Required properties: + - compatible: value should be one of the following: + "atmel,hlcdc-pwm" + - pinctr-names: the pin control state names. Should contain "default". + - pinctrl-0: should contain the pinctrl states described by pinctrl + default. + - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells + bindings defined in Documentation/devicetree/bindings/pwm/pwm.txt. + The first cell encodes the PWM id (0 is the only acceptable value here, + because the chip only provide one PWM). + The second cell encodes the PWM period in nanoseconds. + The third cell encodes the PWM flags (the only supported flag is + PWM_POLARITY_INVERTED) + +Example: + + hlcdc: hlcdc@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + };