| Message ID | 1415660963-17467-1-git-send-email-bob.j.paauwe@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Bob, Thanks for the patch. Just a small comment below. On 11/11/2014 01:09 AM, Bob Paauwe wrote: > Use the new pipe config values to calculate the updated pll dividers. > > This regression was introduced in > > commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59 > Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > Date: Wed Oct 29 11:32:33 2014 +0200 > > drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs > > and > > commit 00d958817dd3daaa452c221387ddaf23d1e4c06f > Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > Date: Wed Oct 29 11:32:36 2014 +0200 > > drm/i915: Covert remaining platforms to choose DPLLS before disabling CRTCs > > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> > CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > CC: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index ff071a7..601641d 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5730,24 +5730,24 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc, > u32 fp, fp2 = 0; > > if (IS_PINEVIEW(dev)) { > - fp = pnv_dpll_compute_fp(&crtc->config.dpll); > + fp = pnv_dpll_compute_fp(&crtc->new_config->dpll); > if (reduced_clock) > fp2 = pnv_dpll_compute_fp(reduced_clock); > } else { > - fp = i9xx_dpll_compute_fp(&crtc->config.dpll); > + fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); > if (reduced_clock) > fp2 = i9xx_dpll_compute_fp(reduced_clock); > } > > - crtc->config.dpll_hw_state.fp0 = fp; > + crtc->new_config->dpll_hw_state.fp0 = fp; > > crtc->lowfreq_avail = false; > if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && This needs to be changed to intel_pipe_will_have_type(), so that it looks at the new configuration instead of the current one. With that fixed, Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > reduced_clock && i915.powersave) { > - crtc->config.dpll_hw_state.fp1 = fp2; > + crtc->new_config->dpll_hw_state.fp1 = fp2; > crtc->lowfreq_avail = true; > } else { > - crtc->config.dpll_hw_state.fp1 = fp; > + crtc->new_config->dpll_hw_state.fp1 = fp; > } > } > >
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=247/348->277/348
PNV: pass/total=326/328->328/328
ILK: pass/total=329/330->326/330
IVB: pass/total=544/546->545/546
SNB: pass/total=558/563->559/563
HSW: pass/total=572/577->572/577
BDW: pass/total=435/435->434/435
-------------------------------------Detailed-------------------------------------
test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)...
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-basic, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-blt, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-bsd, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-debugfs-entry, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-sysfs-entry, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-ctx-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-blt, BLACKLIST(1, M31)DMESG_WARN(7, M31M36M29)PASS(8, M31M36M38) -> DMESG_WARN(2, M36)PASS(2, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-bsd, BLACKLIST(1, M31)DMESG_WARN(6, M36M29)PASS(9, M31M29M38M36) -> DMESG_WARN(2, M36)PASS(2, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-ctx-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-blt, BLACKLIST(1, M31)DMESG_WARN(7, M31M36M29)PASS(8, M31M36M29M38) -> DMESG_WARN(2, M36)PASS(2, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-bsd, BLACKLIST(1, M31)DMESG_WARN(7, M31M36M29)PASS(8, M31M36M29M38) -> DMESG_WARN(3, M36)PASS(1, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-blt, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-bsd, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_params, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_params-ctx-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-blt, BLACKLIST(1, M31)DMESG_WARN(10, M31M36M29)PASS(5, M29M38M36) -> DMESG_WARN(3, M36)PASS(1, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-bsd, BLACKLIST(1, M31)DMESG_WARN(10, M31M36M29)PASS(5, M36M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-ctx-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-blt, BLACKLIST(1, M31)DMESG_WARN(6, M36M29)PASS(9, M31M36M29M38) -> DMESG_WARN(2, M36)PASS(2, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-bsd, BLACKLIST(1, M31)DMESG_WARN(7, M36M29)PASS(8, M31M36M29M38) -> DMESG_WARN(1, M36)PASS(3, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-ctx-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-render, BLACKLIST(1, M31)PASS(14, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_gem_reset_stats_unrelated-ctx-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M36)
BYT: Intel_gpu_tools, igt_drv_hangman_ring-stop-sysfs-entry, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M36)
PNV: Intel_gpu_tools, igt_kms_setmode_invalid-clone-exclusive-crtc, DMESG_WARN(1, M25)PASS(6, M24) -> DMESG_WARN(3, M24)PASS(1, M24)
PNV: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, DMESG_WARN(1, M25)TIMEOUT(7, M7M25M24)PASS(3, M24) -> DMESG_WARN(3, M24)PASS(1, M24)
ILK: Intel_gpu_tools, igt_kms_pipe_crc_basic_bad-nb-words-1, PASS(4, M26) -> DMESG_WARN(1, M26)PASS(3, M26)
ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-fences-interruptible, PASS(4, M26) -> DMESG_WARN(1, M26)PASS(3, M26)
ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-rmfb, PASS(4, M26) -> DMESG_WARN(1, M26)PASS(3, M26)
IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-1, TIMEOUT(1, M34)PASS(9, M21M4) -> PASS(4, M4)
SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-sliding, DMESG_WARN(1, M35)PASS(9, M35M22) -> PASS(4, M35)
BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, PASS(16, M42M30M28) -> DMESG_WARN(1, M28)PASS(3, M28)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ff071a7..601641d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5730,24 +5730,24 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc, u32 fp, fp2 = 0; if (IS_PINEVIEW(dev)) { - fp = pnv_dpll_compute_fp(&crtc->config.dpll); + fp = pnv_dpll_compute_fp(&crtc->new_config->dpll); if (reduced_clock) fp2 = pnv_dpll_compute_fp(reduced_clock); } else { - fp = i9xx_dpll_compute_fp(&crtc->config.dpll); + fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); if (reduced_clock) fp2 = i9xx_dpll_compute_fp(reduced_clock); } - crtc->config.dpll_hw_state.fp0 = fp; + crtc->new_config->dpll_hw_state.fp0 = fp; crtc->lowfreq_avail = false; if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && reduced_clock && i915.powersave) { - crtc->config.dpll_hw_state.fp1 = fp2; + crtc->new_config->dpll_hw_state.fp1 = fp2; crtc->lowfreq_avail = true; } else { - crtc->config.dpll_hw_state.fp1 = fp; + crtc->new_config->dpll_hw_state.fp1 = fp; } }
Use the new pipe config values to calculate the updated pll dividers. This regression was introduced in commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59 Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:33 2014 +0200 drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs and commit 00d958817dd3daaa452c221387ddaf23d1e4c06f Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:36 2014 +0200 drm/i915: Covert remaining platforms to choose DPLLS before disabling CRTCs Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> CC: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_display.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)