Message ID | 1417100521-8483-1-git-send-email-festevam@gmail.com (mailing list archive) |
---|---|
State | Accepted |
Commit | d206f66177ab7cd69d79c7e01b43f45d935f43dd |
Headers | show |
On Thu, Nov 27, 2014 at 01:01:59PM -0200, Fabio Estevam wrote: > From: Fabio Estevam <fabio.estevam@freescale.com> > > According to the sgtl5000 datasheet the MCLK frequency range restriction of > 8 to 27 MHz only applies when the PLL is used - synchronous SYS_MCLK input mode. Applied all, thanks.
diff --git a/sound/soc/mxs/mxs-sgtl5000.c b/sound/soc/mxs/mxs-sgtl5000.c index 7515cd4..6f1916b 100644 --- a/sound/soc/mxs/mxs-sgtl5000.c +++ b/sound/soc/mxs/mxs-sgtl5000.c @@ -49,13 +49,6 @@ static int mxs_sgtl5000_hw_params(struct snd_pcm_substream *substream, break; } - /* Sgtl5000 sysclk should be >= 8MHz and <= 27M */ - if (mclk < 8000000 || mclk > 27000000) { - dev_err(codec_dai->dev, "Invalid mclk frequency: %u.%03uMHz\n", - mclk / 1000000, mclk / 1000 % 1000); - return -EINVAL; - } - /* Set SGTL5000's SYSCLK (provided by SAIF MCLK) */ ret = snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, mclk, 0); if (ret) {