| Message ID | 1417705672-7914-1-git-send-email-michel.thierry@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Dec 04, 2014 at 03:07:52PM +0000, Michel Thierry wrote: > We already have it for chv, but was missing for bdw. > > Signed-off-by: Michel Thierry <michel.thierry@intel.com> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 788e1b6..91ddcd1 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -756,9 +756,11 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) > * workaround for for a possible hang in the unlikely event a TLB > * invalidation occurs during a PSD flush. > */ > + /* WaHdcDisableFetchWhenMasked:bdw */ > /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */ > WA_SET_BIT_MASKED(HDC_CHICKEN0, > HDC_FORCE_NON_COHERENT | > + HDC_DONOT_FETCH_MEM_WHEN_MASKED | > (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> We also seem to miss the w/a name for the "force non-coherent" thing. Can you add that as well? > > /* Wa4x4STCOptimizationDisable:bdw */ > -- > 2.1.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 12/4/2014 3:25 PM, Ville Syrjälä wrote: > On Thu, Dec 04, 2014 at 03:07:52PM +0000, Michel Thierry wrote: >> We already have it for chv, but was missing for bdw. >> >> Signed-off-by: Michel Thierry <michel.thierry@intel.com> >> --- >> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c >> index 788e1b6..91ddcd1 100644 >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c >> @@ -756,9 +756,11 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) >> * workaround for for a possible hang in the unlikely event a TLB >> * invalidation occurs during a PSD flush. >> */ >> + /* WaHdcDisableFetchWhenMasked:bdw */ >> /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */ >> WA_SET_BIT_MASKED(HDC_CHICKEN0, >> HDC_FORCE_NON_COHERENT | >> + HDC_DONOT_FETCH_MEM_WHEN_MASKED | >> (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > We also seem to miss the w/a name for the "force non-coherent" thing. > Can you add that as well? Sure, I'll add the missing _WaForceEnableNonCoherent:bdw_ label >> >> /* Wa4x4STCOptimizationDisable:bdw */ >> -- >> 2.1.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 364/364 364/364
ILK 366/366 366/366
SNB 450/450 450/450
IVB +17 481/498 498/498
BYT 289/289 289/289
HSW 564/564 564/564
BDW 417/417 417/417
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
IVB igt_kms_3d DMESG_WARN(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_cursor_crc_cursor-128x128-onscreen NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_cursor_crc_cursor-128x128-random NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_cursor_crc_cursor-128x128-sliding NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_cursor_crc_cursor-256x256-offscreen NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_cursor_crc_cursor-256x256-onscreen NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_cursor_crc_cursor-256x256-sliding NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_cursor_crc_cursor-64x64-offscreen NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_cursor_crc_cursor-64x64-onscreen NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_cursor_crc_cursor-64x64-random NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_cursor_crc_cursor-64x64-sliding NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_cursor_crc_cursor-size-change NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_fence_pin_leak NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_rotation_crc_primary-rotation NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
IVB igt_kms_rotation_crc_sprite-rotation NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M34)
Note: You need to pay more attention to line start with '*'
On Thu, Dec 04, 2014 at 05:25:56PM +0200, Ville Syrjälä wrote: > On Thu, Dec 04, 2014 at 03:07:52PM +0000, Michel Thierry wrote: > > We already have it for chv, but was missing for bdw. > > > > Signed-off-by: Michel Thierry <michel.thierry@intel.com> > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index 788e1b6..91ddcd1 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -756,9 +756,11 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) > > * workaround for for a possible hang in the unlikely event a TLB > > * invalidation occurs during a PSD flush. > > */ > > + /* WaHdcDisableFetchWhenMasked:bdw */ > > /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */ > > WA_SET_BIT_MASKED(HDC_CHICKEN0, > > HDC_FORCE_NON_COHERENT | > > + HDC_DONOT_FETCH_MEM_WHEN_MASKED | > > (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Queued for -next, thanks for the patch. -Daniel
On 12/5/2014 2:41 PM, Daniel Vetter wrote: > On Thu, Dec 04, 2014 at 05:25:56PM +0200, Ville Syrjälä wrote: >> On Thu, Dec 04, 2014 at 03:07:52PM +0000, Michel Thierry wrote: >>> We already have it for chv, but was missing for bdw. >>> >>> Signed-off-by: Michel Thierry <michel.thierry@intel.com> >>> --- >>> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > Queued for -next, thanks for the patch. > -Daniel Hi Daniel, Thanks for merging the patch, but you picked v1. I sent an updated version adding the missing wa name in that same register, as Ville suggested (1417707632-8656-1-git-send-email-michel.thierry@intel.com). -Michel
On Tue, Dec 09, 2014 at 01:37:21PM +0000, Michel Thierry wrote: > On 12/5/2014 2:41 PM, Daniel Vetter wrote: > >On Thu, Dec 04, 2014 at 05:25:56PM +0200, Ville Syrjälä wrote: > >>On Thu, Dec 04, 2014 at 03:07:52PM +0000, Michel Thierry wrote: > >>>We already have it for chv, but was missing for bdw. > >>> > >>>Signed-off-by: Michel Thierry <michel.thierry@intel.com> > >>>--- > >>> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ > >>> 1 file changed, 2 insertions(+) > >>> > >>Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > >Queued for -next, thanks for the patch. > >-Daniel > > Hi Daniel, > > Thanks for merging the patch, but you picked v1. > I sent an updated version adding the missing wa name in that same register, > as Ville suggested > (1417707632-8656-1-git-send-email-michel.thierry@intel.com). Oops sorry. Unfortunately that is already in the frozen part of dinq history, so can't exchange. Can you please resubmit a new patch with just the missing bits (and Ville's r-b included)? Thanks, Daniel
On 12/10/2014 9:18 AM, Daniel Vetter wrote: > On Tue, Dec 09, 2014 at 01:37:21PM +0000, Michel Thierry wrote: >> On 12/5/2014 2:41 PM, Daniel Vetter wrote: >>> On Thu, Dec 04, 2014 at 05:25:56PM +0200, Ville Syrjälä wrote: >>>> On Thu, Dec 04, 2014 at 03:07:52PM +0000, Michel Thierry wrote: >>>>> We already have it for chv, but was missing for bdw. >>>>> >>>>> Signed-off-by: Michel Thierry <michel.thierry@intel.com> >>>>> --- >>>>> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ >>>>> 1 file changed, 2 insertions(+) >>>>> >>>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> >>> Queued for -next, thanks for the patch. >>> -Daniel >> Hi Daniel, >> >> Thanks for merging the patch, but you picked v1. >> I sent an updated version adding the missing wa name in that same register, >> as Ville suggested >> (1417707632-8656-1-git-send-email-michel.thierry@intel.com). > Oops sorry. Unfortunately that is already in the frozen part of dinq > history, so can't exchange. Can you please resubmit a new patch with just > the missing bits (and Ville's r-b included)? > > Thanks, Daniel Sure, I just sent it. Thanks,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 788e1b6..91ddcd1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -756,9 +756,11 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) * workaround for for a possible hang in the unlikely event a TLB * invalidation occurs during a PSD flush. */ + /* WaHdcDisableFetchWhenMasked:bdw */ /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */ WA_SET_BIT_MASKED(HDC_CHICKEN0, HDC_FORCE_NON_COHERENT | + HDC_DONOT_FETCH_MEM_WHEN_MASKED | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); /* Wa4x4STCOptimizationDisable:bdw */
We already have it for chv, but was missing for bdw. Signed-off-by: Michel Thierry <michel.thierry@intel.com> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ 1 file changed, 2 insertions(+)