| Message ID | 1418224029-20055-3-git-send-email-david.s.gordon@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -2 364/364 362/364
ILK -11 364/366 353/366
SNB -13 448/450 435/450
IVB -11 497/498 486/498
BYT -5 289/289 284/289
HSW -10 563/564 553/564
BDW -7 417/417 410/417
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt_gem_ringfill_blitter PASS(3, M23M25) DMESG_WARN(1, M25)
*PNV igt_gem_ringfill_blitter-interruptible PASS(3, M23M25) DMESG_WARN(1, M25)
*ILK igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_gem_concurrent_blit_prw-bcs-gpu-read-after-write-interruptible PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_kms_flip_nonexisting-fb DMESG_WARN(1, M26)PASS(4, M26) NSPT(1, M26)
*ILK igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-interruptible PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write-interruptible PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_gem_ringfill_blitter PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_gem_ringfill_blitter-interruptible PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_kms_flip_bcs-flip-vs-modeset-interruptible PASS(5, M26) DMESG_WARN(1, M26)
*SNB igt_gem_concurrent_blit_cpu-rcs-gpu-read-after-write-interruptible PASS(3, M35M22) DMESG_WARN(1, M22)
*SNB igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked PASS(3, M35M22) DMESG_WARN(1, M22)
*SNB igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible PASS(3, M35M22) DMESG_WARN(1, M22)
*SNB igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked PASS(2, M35M22) DMESG_WARN(1, M22)
*SNB igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible PASS(3, M35M22) DMESG_WARN(1, M22)
*SNB igt_gem_concurrent_blit_prw-rcs-gpu-read-after-write-forked PASS(3, M35M22) DMESG_WARN(1, M22)
*SNB igt_gem_concurrent_blit_prw-rcs-gpu-read-after-write-interruptible PASS(3, M35M22) DMESG_WARN(1, M22)
*SNB igt_gem_ring_sync_copy_sync-render-blitter-read-write PASS(3, M35M22) DMESG_WARN(1, M22)
*SNB igt_gem_ring_sync_copy_sync-render-blitter-write-read PASS(3, M35M22) DMESG_WARN(1, M22)
*SNB igt_gem_ring_sync_copy_sync-render-blitter-write-write PASS(3, M35M22) DMESG_WARN(1, M22)
*SNB igt_gem_userptr_blits_coherency-sync PASS(3, M35M22) DMESG_WARN(1, M22)
*SNB igt_pm_rps_min-max-config-loaded PASS(3, M35M22) DMESG_WARN(1, M22)
*SNB igt_gem_concurrent_blit_gtt-rcs-gpu-read-after-write-interruptible PASS(3, M35M22) DMESG_WARN(1, M22)
*IVB igt_gem_linear_blits_interruptible PASS(3, M4M34) DMESG_WARN(1, M34)
*IVB igt_gem_linear_blits_normal PASS(3, M4M34) DMESG_WARN(1, M34)
*IVB igt_gem_render_linear_blits PASS(3, M4M34) DMESG_WARN(1, M34)
*IVB igt_gem_render_tiled_blits PASS(3, M4M34) DMESG_WARN(1, M34)
*IVB igt_gem_tiled_blits_interruptible PASS(3, M4M34) DMESG_WARN(1, M34)
*IVB igt_gem_tiled_blits_normal PASS(3, M4M34) DMESG_WARN(1, M34)
*IVB igt_gem_tiled_fence_blits PASS(3, M4M34) DMESG_WARN(1, M34)
*IVB igt_gem_userptr_blits_coherency-sync PASS(2, M4M34) DMESG_WARN(1, M34)
*IVB igt_gem_userptr_blits_coherency-unsync PASS(2, M4M34) DMESG_WARN(1, M34)
*IVB igt_gem_ringfill_blitter PASS(3, M4M34) DMESG_WARN(1, M34)
*IVB igt_gem_ringfill_blitter-interruptible PASS(3, M4M34) DMESG_WARN(1, M34)
*BYT igt_gem_gtt_hog PASS(3, M48M51) DMESG_WARN(1, M51)
*BYT igt_gem_ringfill_blitter PASS(3, M48M51) DMESG_WARN(1, M51)
*BYT igt_gem_ringfill_blitter-interruptible PASS(3, M48M51) DMESG_WARN(1, M51)
*BYT igt_gem_ringfill_render PASS(3, M48M51) DMESG_WARN(1, M51)
*BYT igt_gem_ringfill_render-interruptible PASS(3, M48M51) DMESG_WARN(1, M51)
*HSW igt_gem_linear_blits_interruptible PASS(3, M40M20) DMESG_WARN(1, M40)
*HSW igt_gem_linear_blits_normal PASS(3, M40M20) DMESG_WARN(1, M40)
*HSW igt_gem_render_linear_blits PASS(3, M40M20) DMESG_WARN(1, M40)
*HSW igt_gem_render_tiled_blits PASS(3, M40M20) DMESG_WARN(1, M40)
*HSW igt_gem_tiled_blits_interruptible PASS(3, M40M20) DMESG_WARN(1, M40)
*HSW igt_gem_tiled_blits_normal PASS(3, M40M20) DMESG_WARN(1, M40)
*HSW igt_gem_tiled_fence_blits PASS(3, M40M20) DMESG_WARN(1, M40)
*HSW igt_pm_rps_min-max-config-loaded PASS(3, M40M20) DMESG_WARN(1, M40)
*HSW igt_gem_ringfill_blitter PASS(3, M40M20) DMESG_WARN(1, M40)
*HSW igt_gem_ringfill_blitter-interruptible PASS(3, M40M20) DMESG_WARN(1, M40)
*BDW igt_gem_render_linear_blits TIMEOUT(1, M30)PASS(3, M30M28) DMESG_WARN(1, M28)
*BDW igt_gem_render_tiled_blits TIMEOUT(1, M30)PASS(3, M30M28) DMESG_WARN(1, M28)
*BDW igt_gem_gtt_hog PASS(3, M30M28) DMESG_WARN(1, M28)
*BDW igt_gem_ringfill_blitter PASS(3, M30M28) DMESG_WARN(1, M28)
*BDW igt_gem_ringfill_blitter-interruptible PASS(3, M30M28) DMESG_WARN(1, M28)
*BDW igt_gem_ringfill_render PASS(3, M30M28) DMESG_WARN(1, M28)
*BDW igt_gem_ringfill_render-interruptible PASS(3, M30M28) DMESG_WARN(1, M28)
Note: You need to pay more attention to line start with '*'
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index a10d271..71cb3ef 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -416,8 +416,17 @@ static inline void __intel_ringbuffer_begin(struct intel_ringbuffer *ringbuf, WARN_ON(nbytes <= 0); if (ringbuf->rsv_level++) { - /* begin() called twice or more without advance() */ - WARN_ON(1); + /* + * A nested reservation; check that it falls entirely + * within the outer block. Don't adjust remaining space. + */ + WARN_ON(ringbuf->rsv_start < 0); + WARN_ON(ringbuf->rsv_start & 7); + WARN_ON(ringbuf->tail & 7); + WARN_ON(ringbuf->tail > ringbuf->effective_size); + WARN_ON(ringbuf->tail > ringbuf->rsv_start + ringbuf->rsv_size); + WARN_ON(ringbuf->tail + nbytes > ringbuf->effective_size); + WARN_ON(ringbuf->tail + nbytes > ringbuf->rsv_start + ringbuf->rsv_size); } else { /* * A new reservation; validate and record the start and @@ -437,7 +446,7 @@ static inline void __intel_ringbuffer_begin(struct intel_ringbuffer *ringbuf, static inline void __intel_ringbuffer_check(struct intel_ringbuffer *ringbuf) { #if 1 - WARN_ON(ringbuf->rsv_level-- != 1); + WARN_ON(ringbuf->rsv_level-- <= 0); WARN_ON(ringbuf->rsv_start < 0 || ringbuf->rsv_size < 0); WARN_ON(ringbuf->tail & 7); WARN_ON(ringbuf->tail > ringbuf->rsv_start + ringbuf->rsv_size);
With the current deferred-submission model, if a problem arises part-way through the insertion of instructions into the ringbuffer (e.g. due to one of the begin() calls finding there's not enough space), we avoid sending the incomplete sequence to the h/w; but currently have no means of undoing the work so far, which will lead to undefined behaviour when the next batch is submitted (probably TDR will trigger a reset first, though, and clean up the ring state). A future idea is to move to an atomic-submission model, where all the space required for a batch submission is reserved up front, and in the event of failure partway through, the work can be abandoned without side-effects. This will be required for the forthcoming GPU scheduler (specifically, for preemption). To support this, we allow nested begin/advance pairs. Specifically, the outermost pair defines the total space reservation; inner pairs can be nested ad lib, but all inner reservations at any level must fit entirely within the outermost one. Thus, this is permitted: begin(128) - guarantees that up to 128 dwords can now be emitted without waiting for more freespace begin(6) advance begin(10) advance begin(8) advance etc, as long as the total is no more than 128 dwords advance-and-submit The execbuffer code will later be enhanced to use this approach. In the mean time, the traditional single-level begin/advance mechanism remains fully supported. This commit changes only the begin/advance checking code, to permit (but not require) nested begin/advance pairs. Signed-off-by: Dave Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/intel_ringbuffer.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)