ARM: shmobile: r8a7790: add MLB+ clock

Message ID	2277336.BnuIY8UiP8@wasted.cogentembedded.com (mailing list archive)
State	Accepted
Commit	f6b5dd4088d082b53eb135e1d6b4b213bf5ce127
Delegated to:	Simon Horman
Headers	show Return-Path: <linux-sh-owner@kernel.org> From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> To: horms@verge.net.au, linux-sh@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org Cc: magnus.damm@gmail.com, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: shmobile: r8a7790: add MLB+ clock Date: Thu, 18 Dec 2014 23:41:52 +0300 Message-ID: <2277336.BnuIY8UiP8@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.3 (Linux/3.17.6-200.fc20.x86_64; KDE/4.14.3; x86_64; ; ) MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-sh-owner@vger.kernel.org Precedence: bulk

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2277336.BnuIY8UiP8@wasted.cogentembedded.com (mailing list archive)

State

Accepted

Commit

f6b5dd4088d082b53eb135e1d6b4b213bf5ce127

Delegated to:

Simon Horman

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From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
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	linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: shmobile: r8a7790: add MLB+ clock
Date: Thu, 18 Dec 2014 23:41:52 +0300
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Commit Message

Sergei Shtylyov Dec. 18, 2014, 8:41 p.m. UTC

From: Andrey Gusakov <andrey.gusakov@cogentembedded.com>

Add MLB+ clock to R8A7790 device tree.

Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
[Sergei: rebased, renamed, added changelog]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
This patch is against 'renesas-devel-20141218-v3.18' tag of Simon Horman's
'renesas.git' repo.

 arch/arm/boot/dts/r8a7790.dtsi            |   13 +++++++------
 include/dt-bindings/clock/r8a7790-clock.h |    1 +
 2 files changed, 8 insertions(+), 6 deletions(-)


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Comments

Simon Horman Dec. 22, 2014, 12:06 a.m. UTC | #1

On Thu, Dec 18, 2014 at 11:41:52PM +0300, Sergei Shtylyov wrote:
> From: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
> 
> Add MLB+ clock to R8A7790 device tree.
> 
> Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
> [Sergei: rebased, renamed, added changelog]
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> 
> ---
> This patch is against 'renesas-devel-20141218-v3.18' tag of Simon Horman's
> 'renesas.git' repo.

Thanks, I have queued this up.

> 
>  arch/arm/boot/dts/r8a7790.dtsi            |   13 +++++++------
>  include/dt-bindings/clock/r8a7790-clock.h |    1 +
>  2 files changed, 8 insertions(+), 6 deletions(-)
> 
> Index: renesas/arch/arm/boot/dts/r8a7790.dtsi
> ===================================================================
> --- renesas.orig/arch/arm/boot/dts/r8a7790.dtsi
> +++ renesas/arch/arm/boot/dts/r8a7790.dtsi
> @@ -1149,16 +1149,17 @@
>  		mstp8_clks: mstp8_clks@e6150990 {
>  			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
>  			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
> -			clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
> -				 <&zs_clk>, <&zs_clk>;
> +			clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
> +			         <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
>  			#clock-cells = <1>;
>  			clock-indices = <
> -				R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
> -				R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
> -				R8A7790_CLK_SATA0
> +				R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
> +				R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
> +				R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
>  			>;
>  			clock-output-names =
> -				"vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
> +				"mlb", "vin3", "vin2", "vin1", "vin0", "ether",
> +				"sata1", "sata0";
>  		};
>  		mstp9_clks: mstp9_clks@e6150994 {
>  			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
> Index: renesas/include/dt-bindings/clock/r8a7790-clock.h
> ===================================================================
> --- renesas.orig/include/dt-bindings/clock/r8a7790-clock.h
> +++ renesas/include/dt-bindings/clock/r8a7790-clock.h
> @@ -97,6 +97,7 @@
>  #define R8A7790_CLK_LVDS0		26
>  
>  /* MSTP8 */
> +#define R8A7790_CLK_MLB		2
>  #define R8A7790_CLK_VIN3		8
>  #define R8A7790_CLK_VIN2		9
>  #define R8A7790_CLK_VIN1		10
> 
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Sergei Shtylyov Dec. 22, 2014, 9:43 p.m. UTC | #2

On 12/22/2014 03:06 AM, Simon Horman wrote:

>> From: Andrey Gusakov <andrey.gusakov@cogentembedded.com>

>> Add MLB+ clock to R8A7790 device tree.

>> Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
>> [Sergei: rebased, renamed, added changelog]
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

>> ---
>> This patch is against 'renesas-devel-20141218-v3.18' tag of Simon Horman's
>> 'renesas.git' repo.

> Thanks, I have queued this up.

    Oops, just saw a formatting issue in this patch...

[...]
>> Index: renesas/include/dt-bindings/clock/r8a7790-clock.h
>> ===================================================================
>> --- renesas.orig/include/dt-bindings/clock/r8a7790-clock.h
>> +++ renesas/include/dt-bindings/clock/r8a7790-clock.h
>> @@ -97,6 +97,7 @@
>>   #define R8A7790_CLK_LVDS0		26
>>
>>   /* MSTP8 */
>> +#define R8A7790_CLK_MLB		2

    Need one more tab here.

>>   #define R8A7790_CLK_VIN3		8
>>   #define R8A7790_CLK_VIN2		9
>>   #define R8A7790_CLK_VIN1		10

    Perhaps you still can fix it up, or I can resend? I'm not seeing this 
patch in the 'devel' branch yet...

WBR, Sergei

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Simon Horman Dec. 23, 2014, 12:23 a.m. UTC | #3

Hi Sergei,

On Tue, Dec 23, 2014 at 12:43:13AM +0300, Sergei Shtylyov wrote:
> On 12/22/2014 03:06 AM, Simon Horman wrote:
> 
> >>From: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
> 
> >>Add MLB+ clock to R8A7790 device tree.
> 
> >>Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
> >>[Sergei: rebased, renamed, added changelog]
> >>Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> 
> >>---
> >>This patch is against 'renesas-devel-20141218-v3.18' tag of Simon Horman's
> >>'renesas.git' repo.
> 
> >Thanks, I have queued this up.
> 
>    Oops, just saw a formatting issue in this patch...
> 
> [...]
> >>Index: renesas/include/dt-bindings/clock/r8a7790-clock.h
> >>===================================================================
> >>--- renesas.orig/include/dt-bindings/clock/r8a7790-clock.h
> >>+++ renesas/include/dt-bindings/clock/r8a7790-clock.h
> >>@@ -97,6 +97,7 @@
> >>  #define R8A7790_CLK_LVDS0		26
> >>
> >>  /* MSTP8 */
> >>+#define R8A7790_CLK_MLB		2
> 
>    Need one more tab here.
> 
> >>  #define R8A7790_CLK_VIN3		8
> >>  #define R8A7790_CLK_VIN2		9
> >>  #define R8A7790_CLK_VIN1		10
> 
>    Perhaps you still can fix it up, or I can resend? I'm not seeing this
> patch in the 'devel' branch yet...

Thanks for following up on this.

I had the patch queued up locally but it seems that I forgot to push them.

I have fixed up this patch by adding an extra tab and pushed the result.
The result should be in renesas-devel-20141223-v3.19-rc1
(But kernel.org seems slow today).

Please let me know if I messed things up somehow.
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Index: renesas/arch/arm/boot/dts/r8a7790.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7790.dtsi
+++ renesas/arch/arm/boot/dts/r8a7790.dtsi
@@ -1149,16 +1149,17 @@ 
 		mstp8_clks: mstp8_clks@e6150990 {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
-			clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
-				 <&zs_clk>, <&zs_clk>;
+			clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
+			         <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
 			#clock-cells = <1>;
 			clock-indices = <
-				R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
-				R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
-				R8A7790_CLK_SATA0
+				R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
+				R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
+				R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
 			>;
 			clock-output-names =
-				"vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
+				"mlb", "vin3", "vin2", "vin1", "vin0", "ether",
+				"sata1", "sata0";
 		};
 		mstp9_clks: mstp9_clks@e6150994 {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
Index: renesas/include/dt-bindings/clock/r8a7790-clock.h
===================================================================
--- renesas.orig/include/dt-bindings/clock/r8a7790-clock.h
+++ renesas/include/dt-bindings/clock/r8a7790-clock.h
@@ -97,6 +97,7 @@ 
 #define R8A7790_CLK_LVDS0		26
 
 /* MSTP8 */
+#define R8A7790_CLK_MLB		2
 #define R8A7790_CLK_VIN3		8
 #define R8A7790_CLK_VIN2		9
 #define R8A7790_CLK_VIN1		10

ARM: shmobile: r8a7790: add MLB+ clock

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