| Message ID | 1421182013-751-3-git-send-email-kenneth@whitecape.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5578
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -1 353/353 352/353
ILK 355/355 355/355
SNB 400/422 400/422
IVB 487/487 487/487
BYT 296/296 296/296
HSW +22 486/508 508/508
BDW -1 402/402 401/402
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt_gen3_render_linear_blits PASS(3, M25M23) CRASH(1, M23)
HSW igt_kms_cursor_crc_cursor-size-change NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_kms_fence_pin_leak NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_kms_flip_event_leak NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_lpsp_non-edp NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_cursor NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_cursor-dpms NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_dpms-mode-unset-non-lpsp NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_dpms-non-lpsp NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_drm-resources-equal NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_fences NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_fences-dpms NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_gem-execbuf NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_gem-mmap-cpu NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_gem-mmap-gtt NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_gem-pread NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_i2c NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_modeset-non-lpsp NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_modeset-non-lpsp-stress-no-wait NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_pci-d3-state NSPT(1, M40)PASS(2, M20) PASS(1, M20)
HSW igt_pm_rpm_rte NSPT(1, M40)PASS(2, M20) PASS(1, M20)
*BDW igt_gem_concurrent_blit_gtt-rcs-early-read-interruptible PASS(5, M30M28) DMESG_WARN(1, M28)
Note: You need to pay more attention to line start with '*'
On Tue, Jan 13, 2015 at 12:46:53PM -0800, Kenneth Graunke wrote: > This is an important optimization for avoiding read-after-write (RAW) > stalls in the HiZ buffer. Certain workloads would run very slowly with > HiZ enabled, but run much faster with the "hiz=false" driconf option. > With this patch, they run at full speed even with HiZ. > > Increases performance in OglVSInstancing by about 2.7x on Braswell. > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> also for the remaining two patches. > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ > 1 file changed, 5 insertions(+) > > Split, as requested by Ben. > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 0df15a4..23020d6 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -846,6 +846,11 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) > HDC_FORCE_NON_COHERENT | > HDC_DONOT_FETCH_MEM_WHEN_MASKED); > > + /* According to the CACHE_MODE_0 default value documentation, some > + * CHV platforms disable this optimization by default. Turn it on. > + */ > + WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); > + > /* Improve HiZ throughput on CHV. */ > WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); > > -- > 2.2.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 0df15a4..23020d6 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -846,6 +846,11 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) HDC_FORCE_NON_COHERENT | HDC_DONOT_FETCH_MEM_WHEN_MASKED); + /* According to the CACHE_MODE_0 default value documentation, some + * CHV platforms disable this optimization by default. Turn it on. + */ + WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); + /* Improve HiZ throughput on CHV. */ WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
This is an important optimization for avoiding read-after-write (RAW) stalls in the HiZ buffer. Certain workloads would run very slowly with HiZ enabled, but run much faster with the "hiz=false" driconf option. With this patch, they run at full speed even with HiZ. Increases performance in OglVSInstancing by about 2.7x on Braswell. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ 1 file changed, 5 insertions(+) Split, as requested by Ben.