diff mbox

drm/i915/bdw: Add support for DRRS to switch RR

Message ID 1421944848-10965-1-git-send-email-ramalingam.c@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ramalingam C Jan. 22, 2015, 4:40 p.m. UTC 
From: Vandana Kannan <vandana.kannan@intel.com>

For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next frame
that is output.

V2: [By Ram]: intel_dp_set_m_n() is rewritten to accommodate
	gen >= 8 [Rodrigo]
V3: Coding style correction [Ram]

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   36 ++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_dp.c      |   16 +++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h     |   11 ++++++++++-
 3 files changed, 47 insertions(+), 16 deletions(-)

Comments

Rodrigo Vivi Jan. 24, 2015, midnight UTC | #1 
On Thu, Jan 22, 2015 at 8:40 AM, Ramalingam C <ramalingam.c@intel.com> wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
>
> For Broadwell, there is one instance of Transcoder MN values per transcoder.
> For dynamic switching between multiple refreshr rates, M/N values may be
> reprogrammed on the fly. Link N programming triggers update of all data and
> link M & N registers and the new M/N values will be used in the next frame
> that is output.
>
> V2: [By Ram]: intel_dp_set_m_n() is rewritten to accommodate
>         gen >= 8 [Rodrigo]
> V3: Coding style correction [Ram]
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   36 ++++++++++++++++++++++------------
>  drivers/gpu/drm/i915/intel_dp.c      |   16 +++++++++++++--
>  drivers/gpu/drm/i915/intel_drv.h     |   11 ++++++++++-
>  3 files changed, 47 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 01dc80b..5712686 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -88,9 +88,6 @@ static int intel_framebuffer_init(struct drm_device *dev,
>                                   struct drm_i915_gem_object *obj);
>  static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
>  static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> -                                        struct intel_link_m_n *m_n,
> -                                        struct intel_link_m_n *m2_n2);

I believe all this set_m_n changes should be in a separated
preparation patch....

>  static void ironlake_set_pipeconf(struct drm_crtc *crtc);
>  static void haswell_set_pipeconf(struct drm_crtc *crtc);
>  static void intel_set_pipe_csc(struct drm_crtc *crtc);
> @@ -4289,7 +4286,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>                 intel_prepare_shared_dpll(intel_crtc);
>
>         if (intel_crtc->config->has_dp_encoder)
> -               intel_dp_set_m_n(intel_crtc);
> +               intel_dp_set_m_n(intel_crtc, M1_N1);
>
>         intel_set_pipe_timings(intel_crtc);
>
> @@ -4397,7 +4394,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>                 intel_enable_shared_dpll(intel_crtc);
>
>         if (intel_crtc->config->has_dp_encoder)
> -               intel_dp_set_m_n(intel_crtc);
> +               intel_dp_set_m_n(intel_crtc, M1_N1);
>
>         intel_set_pipe_timings(intel_crtc);
>
> @@ -5011,7 +5008,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>         }
>
>         if (intel_crtc->config->has_dp_encoder)
> -               intel_dp_set_m_n(intel_crtc);
> +               intel_dp_set_m_n(intel_crtc, M1_N1);
>
>         intel_set_pipe_timings(intel_crtc);
>
> @@ -5087,7 +5084,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>         i9xx_set_pll_dividers(intel_crtc);
>
>         if (intel_crtc->config->has_dp_encoder)
> -               intel_dp_set_m_n(intel_crtc);
> +               intel_dp_set_m_n(intel_crtc, M1_N1);
>
>         intel_set_pipe_timings(intel_crtc);
>
> @@ -5828,9 +5825,9 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
>         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
>  }
>
> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> -                                        struct intel_link_m_n *m_n,
> -                                        struct intel_link_m_n *m2_n2)
> +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> +                                struct intel_link_m_n *m_n,
> +                                struct intel_link_m_n *m2_n2)
>  {
>         struct drm_device *dev = crtc->base.dev;
>         struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -5862,13 +5859,26 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>         }
>  }
>
> -void intel_dp_set_m_n(struct intel_crtc *crtc)
> +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
>  {
> +       struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
> +
> +       if (m_n == M1_N1) {
> +               dp_m_n = &crtc->config->dp_m_n;
> +               dp_m2_n2 = &crtc->config->dp_m2_n2;
> +       } else if (m_n == M2_N2) {
> +               /* Only one register programming is supported. And m_n value
> +                * corresponding to downclock mode needs to be programmed */
> +               dp_m_n = &crtc->config->dp_m2_n2;
> +       } else {
> +               DRM_ERROR("Unsupported divider value\n");
> +               return;
> +       }
> +
>         if (crtc->config->has_pch_encoder)
>                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
>         else
> -               intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
> -                                                  &crtc->config->dp_m2_n2);
> +               intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
>  }
>
>  static void vlv_update_pll(struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 955aca3..27ff0d4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4803,12 +4803,24 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>                 return;
>         }
>
> -       if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
> +       if (INTEL_INFO(dev)->gen >= 8) {
> +               switch (index) {
> +               case DRRS_HIGH_RR:
> +                       intel_dp_set_m_n(intel_crtc, M1_N1);
> +                       break;
> +               case DRRS_LOW_RR:
> +                       intel_dp_set_m_n(intel_crtc, M2_N2);
> +                       break;
> +               case DRRS_MAX_RR:
> +               default:
> +                       DRM_ERROR("Unsupported refreshrate type\n");
> +               }
> +       } else if (INTEL_INFO(dev)->gen > 6) {
>                 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
>                 val = I915_READ(reg);
> +

Then, only this block really related to drrs as in commit message
should stay on this commit.

>                 if (index > DRRS_HIGH_RR) {
>                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
> -                       intel_dp_set_m_n(intel_crtc);
>                 } else {
>                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
>                 }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index a31dc103..193ccda 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -587,6 +587,12 @@ struct intel_hdmi {
>  struct intel_dp_mst_encoder;
>  #define DP_MAX_DOWNSTREAM_PORTS                0x10
>
> +/* enum to indicate the m_n value from calculated list */
> +enum link_m_n_set {
> +       M1_N1 = 0,
> +       M2_N2
> +};
> +
>  struct intel_dp {
>         uint32_t output_reg;
>         uint32_t aux_ch_ctl_reg;
> @@ -979,7 +985,10 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
>  void hsw_disable_pc8(struct drm_i915_private *dev_priv);
>  void intel_dp_get_m_n(struct intel_crtc *crtc,
>                       struct intel_crtc_state *pipe_config);
> -void intel_dp_set_m_n(struct intel_crtc *crtc);
> +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
> +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> +                                struct intel_link_m_n *m_n,
> +                                struct intel_link_m_n *m2_n2);
>  int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
>  void
>  ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

but I don't want to block progress here....
I'll let this desicion to author and maintainer and in any case feel free to
use my:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 01dc80b..5712686 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -88,9 +88,6 @@  static int intel_framebuffer_init(struct drm_device *dev,
 				  struct drm_i915_gem_object *obj);
 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
-					 struct intel_link_m_n *m_n,
-					 struct intel_link_m_n *m2_n2);
 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 static void intel_set_pipe_csc(struct drm_crtc *crtc);
@@ -4289,7 +4286,7 @@  static void ironlake_crtc_enable(struct drm_crtc *crtc)
 		intel_prepare_shared_dpll(intel_crtc);
 
 	if (intel_crtc->config->has_dp_encoder)
-		intel_dp_set_m_n(intel_crtc);
+		intel_dp_set_m_n(intel_crtc, M1_N1);
 
 	intel_set_pipe_timings(intel_crtc);
 
@@ -4397,7 +4394,7 @@  static void haswell_crtc_enable(struct drm_crtc *crtc)
 		intel_enable_shared_dpll(intel_crtc);
 
 	if (intel_crtc->config->has_dp_encoder)
-		intel_dp_set_m_n(intel_crtc);
+		intel_dp_set_m_n(intel_crtc, M1_N1);
 
 	intel_set_pipe_timings(intel_crtc);
 
@@ -5011,7 +5008,7 @@  static void valleyview_crtc_enable(struct drm_crtc *crtc)
 	}
 
 	if (intel_crtc->config->has_dp_encoder)
-		intel_dp_set_m_n(intel_crtc);
+		intel_dp_set_m_n(intel_crtc, M1_N1);
 
 	intel_set_pipe_timings(intel_crtc);
 
@@ -5087,7 +5084,7 @@  static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	i9xx_set_pll_dividers(intel_crtc);
 
 	if (intel_crtc->config->has_dp_encoder)
-		intel_dp_set_m_n(intel_crtc);
+		intel_dp_set_m_n(intel_crtc, M1_N1);
 
 	intel_set_pipe_timings(intel_crtc);
 
@@ -5828,9 +5825,9 @@  static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
 	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
 }
 
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
-					 struct intel_link_m_n *m_n,
-					 struct intel_link_m_n *m2_n2)
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+				 struct intel_link_m_n *m_n,
+				 struct intel_link_m_n *m2_n2)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5862,13 +5859,26 @@  static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 	}
 }
 
-void intel_dp_set_m_n(struct intel_crtc *crtc)
+void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
 {
+	struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
+
+	if (m_n == M1_N1) {
+		dp_m_n = &crtc->config->dp_m_n;
+		dp_m2_n2 = &crtc->config->dp_m2_n2;
+	} else if (m_n == M2_N2) {
+		/* Only one register programming is supported. And m_n value
+		 * corresponding to downclock mode needs to be programmed */
+		dp_m_n = &crtc->config->dp_m2_n2;
+	} else {
+		DRM_ERROR("Unsupported divider value\n");
+		return;
+	}
+
 	if (crtc->config->has_pch_encoder)
 		intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
 	else
-		intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
-						   &crtc->config->dp_m2_n2);
+		intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
 }
 
 static void vlv_update_pll(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 955aca3..27ff0d4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4803,12 +4803,24 @@  static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 		return;
 	}
 
-	if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
+	if (INTEL_INFO(dev)->gen >= 8) {
+		switch (index) {
+		case DRRS_HIGH_RR:
+			intel_dp_set_m_n(intel_crtc, M1_N1);
+			break;
+		case DRRS_LOW_RR:
+			intel_dp_set_m_n(intel_crtc, M2_N2);
+			break;
+		case DRRS_MAX_RR:
+		default:
+			DRM_ERROR("Unsupported refreshrate type\n");
+		}
+	} else if (INTEL_INFO(dev)->gen > 6) {
 		reg = PIPECONF(intel_crtc->config->cpu_transcoder);
 		val = I915_READ(reg);
+
 		if (index > DRRS_HIGH_RR) {
 			val |= PIPECONF_EDP_RR_MODE_SWITCH;
-			intel_dp_set_m_n(intel_crtc);
 		} else {
 			val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
 		}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a31dc103..193ccda 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -587,6 +587,12 @@  struct intel_hdmi {
 struct intel_dp_mst_encoder;
 #define DP_MAX_DOWNSTREAM_PORTS		0x10
 
+/* enum to indicate the m_n value from calculated list */
+enum link_m_n_set {
+	M1_N1 = 0,
+	M2_N2
+};
+
 struct intel_dp {
 	uint32_t output_reg;
 	uint32_t aux_ch_ctl_reg;
@@ -979,7 +985,10 @@  void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
 		      struct intel_crtc_state *pipe_config);
-void intel_dp_set_m_n(struct intel_crtc *crtc);
+void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+				 struct intel_link_m_n *m_n,
+				 struct intel_link_m_n *m2_n2);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 void
 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,