| Message ID | 1418235132-23601-1-git-send-email-david.s.gordon@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Dave Gordon <david.s.gordon@intel.com> writes: > When querying the GTFIFOCTL register to check the FIFO space, the read value > must be masked. The operation is repeated explicitly in several places. This > change refactors the read-and-mask code into a function call. > > v2: rebased on top of Mika's forcewake patch set, specifically: > [PATCH 8/8] drm/i915: Enum forcewake domains and domain identifiers > > Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef > Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/intel_uncore.c | 19 ++++++++++++------- > 1 file changed, 12 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 66365e7..a0331a7 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -205,6 +205,13 @@ static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, > gen6_gt_check_fifodbg(dev_priv); > } > > +static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) > +{ > + u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); > + > + return count & GT_FIFO_FREE_ENTRIES_MASK; > +} > + > static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) > { > int ret = 0; > @@ -212,16 +219,15 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) > /* On VLV, FIFO will be shared by both SW and HW. > * So, we need to read the FREE_ENTRIES everytime */ > if (IS_VALLEYVIEW(dev_priv->dev)) > - dev_priv->uncore.fifo_count = > - __raw_i915_read32(dev_priv, GTFIFOCTL) & > - GT_FIFO_FREE_ENTRIES_MASK; > + dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); > > if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { > int loop = 500; > - u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; > + u32 fifo = fifo_free_entries(dev_priv); > + > while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { > udelay(10); > - fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; > + fifo = fifo_free_entries(dev_priv); > } > if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) > ++ret; > @@ -277,8 +283,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) > > if (IS_GEN6(dev) || IS_GEN7(dev)) > dev_priv->uncore.fifo_count = > - __raw_i915_read32(dev_priv, GTFIFOCTL) & > - GT_FIFO_FREE_ENTRIES_MASK; > + fifo_free_entries(dev_priv); > } > > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Feb 20, 2015 at 11:34:29AM +0200, Mika Kuoppala wrote: > Dave Gordon <david.s.gordon@intel.com> writes: > > > When querying the GTFIFOCTL register to check the FIFO space, the read value > > must be masked. The operation is repeated explicitly in several places. This > > change refactors the read-and-mask code into a function call. > > > > v2: rebased on top of Mika's forcewake patch set, specifically: > > [PATCH 8/8] drm/i915: Enum forcewake domains and domain identifiers > > > > Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef > > Signed-off-by: Dave Gordon <david.s.gordon@intel.com> > > Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 66365e7..a0331a7 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -205,6 +205,13 @@ static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, gen6_gt_check_fifodbg(dev_priv); } +static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) +{ + u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); + + return count & GT_FIFO_FREE_ENTRIES_MASK; +} + static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) { int ret = 0; @@ -212,16 +219,15 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) /* On VLV, FIFO will be shared by both SW and HW. * So, we need to read the FREE_ENTRIES everytime */ if (IS_VALLEYVIEW(dev_priv->dev)) - dev_priv->uncore.fifo_count = - __raw_i915_read32(dev_priv, GTFIFOCTL) & - GT_FIFO_FREE_ENTRIES_MASK; + dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { int loop = 500; - u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; + u32 fifo = fifo_free_entries(dev_priv); + while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { udelay(10); - fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; + fifo = fifo_free_entries(dev_priv); } if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) ++ret; @@ -277,8 +283,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) if (IS_GEN6(dev) || IS_GEN7(dev)) dev_priv->uncore.fifo_count = - __raw_i915_read32(dev_priv, GTFIFOCTL) & - GT_FIFO_FREE_ENTRIES_MASK; + fifo_free_entries(dev_priv); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
When querying the GTFIFOCTL register to check the FIFO space, the read value must be masked. The operation is repeated explicitly in several places. This change refactors the read-and-mask code into a function call. v2: rebased on top of Mika's forcewake patch set, specifically: [PATCH 8/8] drm/i915: Enum forcewake domains and domain identifiers Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef Signed-off-by: Dave Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-)