| Message ID | 1425061352-29188-2-git-send-email-jeff.mcgee@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Feb 27, 2015 at 10:22:31AM -0800, jeff.mcgee@intel.com wrote: > From: Jeff McGee <jeff.mcgee@intel.com> > > Total EU was already being detected on CHV, so we just add the > additional info parameters. The detection method is changed to > be more robust in the case of subslice fusing - we don't want > to trust the EU fuse bits corresponding to subslices which are > fused-off. > > Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> > --- > drivers/gpu/drm/i915/i915_dma.c | 40 ++++++++++++++++++++++++++++++++++------ > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > 2 files changed, 36 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index 053e178..04e5b55e 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -608,14 +608,42 @@ static void intel_device_info_runtime_init(struct drm_device *dev) > > /* Initialize slice/subslice/EU info */ > if (IS_CHERRYVIEW(dev)) { > - u32 fuse, mask_eu; > + u32 fuse, eu_dis; > > fuse = I915_READ(CHV_FUSE_GT); > - mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | > - CHV_FGT_EU_DIS_SS0_R1_MASK | > - CHV_FGT_EU_DIS_SS1_R0_MASK | > - CHV_FGT_EU_DIS_SS1_R1_MASK); > - info->eu_total = 16 - hweight32(mask_eu); > + > + info->slice_total = 1; > + > + if (!(fuse & CHV_FGT_DISABLE_SS0)) { ^^^^^^^^^^^^^^^^^^^ That's your shift value. Masking with it probably won't work :P > + info->subslice_per_slice++; > + eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | > + CHV_FGT_EU_DIS_SS0_R1_MASK); > + info->eu_total += 8 - hweight32(eu_dis); > + } > + > + if (!(fuse & CHV_FGT_DISABLE_SS1)) { ditto > + info->subslice_per_slice++; > + eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | > + CHV_FGT_EU_DIS_SS1_R1_MASK); > + info->eu_total += 8 - hweight32(eu_dis); > + } > + > + info->subslice_total = info->subslice_per_slice; > + /* > + * CHV expected to always have a uniform distribution of EU > + * across subslices. > + */ > + info->eu_per_subslice = info->subslice_total ? > + info->eu_total / info->subslice_total : > + 0; > + /* > + * CHV supports subslice power gating on devices with more than > + * one subslice, and supports EU power gating on devices with > + * more than one EU pair per subslice. > + */ > + info->has_slice_pg = 0; > + info->has_subslice_pg = (info->subslice_total > 1) ? 1 : 0; > + info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0; Nit: use of ?: seems pointless in these. > } else if (IS_SKYLAKE(dev)) { > const int s_max = 3, ss_max = 4, eu_max = 8; > int s, ss; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 55143cb..a8b205d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1522,6 +1522,8 @@ enum skl_disp_power_wells { > > /* Fuse readout registers for GT */ > #define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168) > +#define CHV_FGT_DISABLE_SS0 10 > +#define CHV_FGT_DISABLE_SS1 11 > #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 > #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) > #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 > -- > 2.3.0
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 053e178..04e5b55e 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -608,14 +608,42 @@ static void intel_device_info_runtime_init(struct drm_device *dev) /* Initialize slice/subslice/EU info */ if (IS_CHERRYVIEW(dev)) { - u32 fuse, mask_eu; + u32 fuse, eu_dis; fuse = I915_READ(CHV_FUSE_GT); - mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | - CHV_FGT_EU_DIS_SS0_R1_MASK | - CHV_FGT_EU_DIS_SS1_R0_MASK | - CHV_FGT_EU_DIS_SS1_R1_MASK); - info->eu_total = 16 - hweight32(mask_eu); + + info->slice_total = 1; + + if (!(fuse & CHV_FGT_DISABLE_SS0)) { + info->subslice_per_slice++; + eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | + CHV_FGT_EU_DIS_SS0_R1_MASK); + info->eu_total += 8 - hweight32(eu_dis); + } + + if (!(fuse & CHV_FGT_DISABLE_SS1)) { + info->subslice_per_slice++; + eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | + CHV_FGT_EU_DIS_SS1_R1_MASK); + info->eu_total += 8 - hweight32(eu_dis); + } + + info->subslice_total = info->subslice_per_slice; + /* + * CHV expected to always have a uniform distribution of EU + * across subslices. + */ + info->eu_per_subslice = info->subslice_total ? + info->eu_total / info->subslice_total : + 0; + /* + * CHV supports subslice power gating on devices with more than + * one subslice, and supports EU power gating on devices with + * more than one EU pair per subslice. + */ + info->has_slice_pg = 0; + info->has_subslice_pg = (info->subslice_total > 1) ? 1 : 0; + info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0; } else if (IS_SKYLAKE(dev)) { const int s_max = 3, ss_max = 4, eu_max = 8; int s, ss; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 55143cb..a8b205d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1522,6 +1522,8 @@ enum skl_disp_power_wells { /* Fuse readout registers for GT */ #define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168) +#define CHV_FGT_DISABLE_SS0 10 +#define CHV_FGT_DISABLE_SS1 11 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20