| Message ID | 1425667853-5717-2-git-send-email-damien.lespiau@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Mar 06, 2015 at 06:50:48PM +0000, Damien Lespiau wrote: > While we only need to restore pipe B/C interrupt registers on BDW when > enabling the power well, skylake a bit more flexible and we'll also need > to restore the pipe A registers as it has its own power well that can be > toggled. > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++++----- > drivers/gpu/drm/i915/intel_drv.h | 3 ++- > drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ++- > 3 files changed, 14 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 9baecb7..d77a4b6 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -3169,15 +3169,20 @@ static void gen8_irq_reset(struct drm_device *dev) > ibx_irq_reset(dev); > } > > -void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) > +void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, > + unsigned int pipe_mask) > { > uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; > > spin_lock_irq(&dev_priv->irq_lock); > - GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], > - ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); > - GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], > - ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); > + if (pipe_mask & 1 << PIPE_B) > + GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, > + dev_priv->de_irq_mask[PIPE_B], > + ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); > + if (pipe_mask & 1 << PIPE_C) > + GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, > + dev_priv->de_irq_mask[PIPE_C], > + ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); > spin_unlock_irq(&dev_priv->irq_lock); Since this now takes a pipe mask I really think we should eventually move this as a call into the gen8+ crtc enable code ... -Daniel > } > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index ff79dca..c77128c 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -840,7 +840,8 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) > } > > int intel_get_crtc_scanline(struct intel_crtc *crtc); > -void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv); > +void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, > + unsigned int pipe_mask); > > /* intel_crt.c */ > void intel_crt_init(struct drm_device *dev); > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 6d8e29a..35e0cb6 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -195,7 +195,8 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) > vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); > > if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9)) > - gen8_irq_power_well_post_enable(dev_priv); > + gen8_irq_power_well_post_enable(dev_priv, > + 1 << PIPE_C | 1 << PIPE_B); > } > > static void hsw_set_power_well(struct drm_i915_private *dev_priv, > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 9baecb7..d77a4b6 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3169,15 +3169,20 @@ static void gen8_irq_reset(struct drm_device *dev) ibx_irq_reset(dev); } -void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) +void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, + unsigned int pipe_mask) { uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; spin_lock_irq(&dev_priv->irq_lock); - GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], - ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); - GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], - ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); + if (pipe_mask & 1 << PIPE_B) + GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, + dev_priv->de_irq_mask[PIPE_B], + ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); + if (pipe_mask & 1 << PIPE_C) + GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, + dev_priv->de_irq_mask[PIPE_C], + ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); spin_unlock_irq(&dev_priv->irq_lock); } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ff79dca..c77128c 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -840,7 +840,8 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) } int intel_get_crtc_scanline(struct intel_crtc *crtc); -void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv); +void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, + unsigned int pipe_mask); /* intel_crt.c */ void intel_crt_init(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 6d8e29a..35e0cb6 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -195,7 +195,8 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9)) - gen8_irq_power_well_post_enable(dev_priv); + gen8_irq_power_well_post_enable(dev_priv, + 1 << PIPE_C | 1 << PIPE_B); } static void hsw_set_power_well(struct drm_i915_private *dev_priv,