| Message ID | 1424880159-29348-8-git-send-email-alex.bennee@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Feb 25, 2015 at 10:02 AM, Alex Bennée <alex.bennee@linaro.org> wrote: > I was getting very confused about the duplication of state. Perhaps we > should just get rid of env->spsr and use helpers that understand the > banking? > > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 11845a6..d7fd13f 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -155,6 +155,11 @@ typedef struct CPUARMState { > This contains all the other bits. Use cpsr_{read,write} to access > the whole CPSR. */ > uint32_t uncached_cpsr; > + /* The spsr is a alias for spsr_elN where N is the current "an alias" > + * exception level. It is provided for here so the TCG msr/mrs remove "for here" > + * implementation can access one register. Care needs to be taken > + * to ensure the banked_spsr[] is also updated. > + */ > uint32_t spsr; > > /* Banked registers. */ > -- > 2.3.0 > > Otherwise... Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
On 25 February 2015 at 16:02, Alex Bennée <alex.bennee@linaro.org> wrote: > I was getting very confused about the duplication of state. Perhaps we > should just get rid of env->spsr and use helpers that understand the > banking? I've already disagreed with this. I would suggest putting tentative questions about future direction of the codebase below the '---' rather than in the commit log :-) > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 11845a6..d7fd13f 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -155,6 +155,11 @@ typedef struct CPUARMState { > This contains all the other bits. Use cpsr_{read,write} to access > the whole CPSR. */ > uint32_t uncached_cpsr; > + /* The spsr is a alias for spsr_elN where N is the current > + * exception level. This isn't true for AArch32 (which has multiple different SPSRs any of which might be the one in env->spsr when we're at EL1). -- PMM
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 11845a6..d7fd13f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -155,6 +155,11 @@ typedef struct CPUARMState { This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ uint32_t uncached_cpsr; + /* The spsr is a alias for spsr_elN where N is the current + * exception level. It is provided for here so the TCG msr/mrs + * implementation can access one register. Care needs to be taken + * to ensure the banked_spsr[] is also updated. + */ uint32_t spsr; /* Banked registers. */
I was getting very confused about the duplication of state. Perhaps we should just get rid of env->spsr and use helpers that understand the banking? Signed-off-by: Alex Bennée <alex.bennee@linaro.org>