| Message ID | 1425620244-12637-4-git-send-email-akash.goel@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Mar 06, 2015 at 11:07:16AM +0530, akash.goel@intel.com wrote: > From: Akash Goel <akash.goel@intel.com> > > On SKL the frequency is specified in units of 16.66 MHZ, barring the > RP_STATE_CAP(0x5998) register, which still reports frequency in units > of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies > function for SKL, to store the frequency values as per the actual hardware unit. > > v2: Corrected the conversion from 50 to 16.66 MHZ (Ville) > > Signed-off-by: Akash Goel <akash.goel@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 1b44eee..81eaa0c 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4080,6 +4080,13 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) > dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; > dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; > dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; > + if (IS_SKYLAKE(dev)) { > + /* Store the frequency values in 16.66 MHZ units, which is > + the natural hardware unit for SKL */ > + dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; > + dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; > + dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; > + } > /* hw_max = RP0 until we check for overclocking */ > dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; > > -- > 1.9.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1b44eee..81eaa0c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4080,6 +4080,13 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; + if (IS_SKYLAKE(dev)) { + /* Store the frequency values in 16.66 MHZ units, which is + the natural hardware unit for SKL */ + dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; + dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; + dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; + } /* hw_max = RP0 until we check for overclocking */ dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;