diff mbox

[v2,1/2] ARM: dts: imx6: factor out pinmux for edm1 module

Message ID 1425831960-10259-1-git-send-email-m.grzeschik@pengutronix.de (mailing list archive)
State New, archived
Headers show

Commit Message

Michael Grzeschik March 8, 2015, 4:25 p.m. UTC 
Thw Wandboard is using the EDM1-CF-IMX6 module which is
defined under the edm standard.

http://www.edm-standard.org/

As this module is used on more boards this patch moves the default
pinmux settings into the special file imx6qdl-edm1.dtsi.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
- fixed the alphabetical order of the nodes
- moved MX6QDL_PAD_GPIO_16__ENET_REF_CLK to the board hogpins

 arch/arm/boot/dts/imx6qdl-edm1.dtsi            | 230 +++++++++++++++++++++++++
 arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi |   1 +
 arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi |   1 +
 arch/arm/boot/dts/imx6qdl-wandboard.dtsi       |  99 +----------
 4 files changed, 234 insertions(+), 97 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx6qdl-edm1.dtsi

Comments

Fabio Estevam March 8, 2015, 8:04 p.m. UTC | #1 
On Sun, Mar 8, 2015 at 1:25 PM, Michael Grzeschik
<m.grzeschik@pengutronix.de> wrote:
> Thw Wandboard is using the EDM1-CF-IMX6 module which is
> defined under the edm standard.
>
> http://www.edm-standard.org/
>
> As this module is used on more boards this patch moves the default
> pinmux settings into the special file imx6qdl-edm1.dtsi.
>
> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> ---
> - fixed the alphabetical order of the nodes
> - moved MX6QDL_PAD_GPIO_16__ENET_REF_CLK to the board hogpins

Adding Alfonso in case he can help testing v2.

Regards,

Fabio Estevam
Michael Grzeschik March 23, 2015, 3:19 p.m. UTC | #2 
On Sun, Mar 08, 2015 at 05:25:59PM +0100, Michael Grzeschik wrote:
> Thw Wandboard is using the EDM1-CF-IMX6 module which is
> defined under the edm standard.
> 
> http://www.edm-standard.org/
> 
> As this module is used on more boards this patch moves the default
> pinmux settings into the special file imx6qdl-edm1.dtsi.
> 
> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> ---
> - fixed the alphabetical order of the nodes
> - moved MX6QDL_PAD_GPIO_16__ENET_REF_CLK to the board hogpins
> 
>  arch/arm/boot/dts/imx6qdl-edm1.dtsi            | 230 +++++++++++++++++++++++++
>  arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi |   1 +
>  arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi |   1 +
>  arch/arm/boot/dts/imx6qdl-wandboard.dtsi       |  99 +----------
>  4 files changed, 234 insertions(+), 97 deletions(-)
>  create mode 100644 arch/arm/boot/dts/imx6qdl-edm1.dtsi

subliminal ping...
Shawn Guo March 24, 2015, 12:18 p.m. UTC | #3 
On Mon, Mar 23, 2015 at 04:19:37PM +0100, Michael Grzeschik wrote:
> On Sun, Mar 08, 2015 at 05:25:59PM +0100, Michael Grzeschik wrote:
> > Thw Wandboard is using the EDM1-CF-IMX6 module which is
> > defined under the edm standard.
> > 
> > http://www.edm-standard.org/
> > 
> > As this module is used on more boards this patch moves the default
> > pinmux settings into the special file imx6qdl-edm1.dtsi.
> > 
> > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> > ---
> > - fixed the alphabetical order of the nodes
> > - moved MX6QDL_PAD_GPIO_16__ENET_REF_CLK to the board hogpins
> > 
> >  arch/arm/boot/dts/imx6qdl-edm1.dtsi            | 230 +++++++++++++++++++++++++
> >  arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi |   1 +
> >  arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi |   1 +
> >  arch/arm/boot/dts/imx6qdl-wandboard.dtsi       |  99 +----------
> >  4 files changed, 234 insertions(+), 97 deletions(-)
> >  create mode 100644 arch/arm/boot/dts/imx6qdl-edm1.dtsi
> 
> subliminal ping...

Have we got anyone test the patch on Wandboard as requested by rsc [1]?

Shawn

[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/394350/focus=394353
Michael Grzeschik March 25, 2015, 3:46 p.m. UTC | #4 
On Tue, Mar 24, 2015 at 08:18:11PM +0800, Shawn Guo wrote:
> On Mon, Mar 23, 2015 at 04:19:37PM +0100, Michael Grzeschik wrote:
> > On Sun, Mar 08, 2015 at 05:25:59PM +0100, Michael Grzeschik wrote:
> > > Thw Wandboard is using the EDM1-CF-IMX6 module which is
> > > defined under the edm standard.
> > > 
> > > http://www.edm-standard.org/
> > > 
> > > As this module is used on more boards this patch moves the default
> > > pinmux settings into the special file imx6qdl-edm1.dtsi.
> > > 
> > > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> > > ---
> > > - fixed the alphabetical order of the nodes
> > > - moved MX6QDL_PAD_GPIO_16__ENET_REF_CLK to the board hogpins
> > > 
> > >  arch/arm/boot/dts/imx6qdl-edm1.dtsi            | 230 +++++++++++++++++++++++++
> > >  arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi |   1 +
> > >  arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi |   1 +
> > >  arch/arm/boot/dts/imx6qdl-wandboard.dtsi       |  99 +----------
> > >  4 files changed, 234 insertions(+), 97 deletions(-)
> > >  create mode 100644 arch/arm/boot/dts/imx6qdl-edm1.dtsi
> > 
> > subliminal ping...
> 
> Have we got anyone test the patch on Wandboard as requested by rsc [1]?

So far, not yet. :/

Could anyone test?

Thanks,
Michael
Fabio Estevam April 7, 2015, 12:54 p.m. UTC | #5 
Hi Michael,

On Sun, Mar 8, 2015 at 1:25 PM, Michael Grzeschik
<m.grzeschik@pengutronix.de> wrote:
> Thw Wandboard is using the EDM1-CF-IMX6 module which is
> defined under the edm standard.
>
> http://www.edm-standard.org/
>
> As this module is used on more boards this patch moves the default
> pinmux settings into the special file imx6qdl-edm1.dtsi.
>
> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>

Sorry for the delay in testing your patch.

Wandboard does not seem very happy about it:

[    7.372909] turning off the locking correctness validator.
[    7.378430] CPU: 3 PID: 0 Comm: swapper/3 Not tainted
4.0.0-rc3-10351-g94a600d-dirty #6
[    7.386460] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
[    7.393011] Backtrace:
[    7.395554] [<80011f0c>] (dump_backtrace) from [<800120a8>]
(show_stack+0x18/0x1c)
[    7.403150]  r6:812a8bac r5:00000000 r4:00000000 r3:00000000
[    7.408983] [<80012090>] (show_stack) from [<80731764>]
(dump_stack+0x88/0xa4)
[    7.416256] [<807316dc>] (dump_stack) from [<80062094>]
(__lock_acquire+0x1858/0x1b84)
[    7.424198]  r5:00000000 r4:ee0a7e48
[    7.427870] [<8006083c>] (__lock_acquire) from [<800628ac>]
(lock_acquire+0x74/0x94)
[    7.435631]  r10:8007aa28 r9:00000000 r8:00000000 r7:00000001
r6:8007aa28 r5:60000113
[    7.443574]  r4:00000000
[    7.446153] [<80062838>] (lock_acquire) from [<8007aa90>]
(call_timer_fn+0x68/0xfc)
[    7.453818]  r7:00000100 r6:00000000 r5:00000001 r4:ee0a7e48
[    7.459578] [<8007aa28>] (call_timer_fn) from [<8007b3ec>]
(run_timer_softirq+0x1c4/0x264)
[    7.467850]  r10:80a5a100 r8:00000000 r7:00000000 r6:ee0a7e88
r5:ee02e000 r4:ed8b0894
[    7.475806] [<8007b228>] (run_timer_softirq) from [<8002d97c>]
(__do_softirq+0x138/0x2c4)
[    7.483991]  r10:80a5a080 r9:00000100 r8:00000001 r7:80a5a080
r6:00000001 r5:80a5a084
[    7.491932]  r4:000000a0
[    7.494499] [<8002d844>] (__do_softirq) from [<8002de50>]
(irq_exit+0xc4/0x138)
[    7.501816]  r10:ee008000 r9:80a5a9c8 r8:00000001 r7:00000000
r6:80a54d7c r5:80a5aaf8
[    7.509758]  r4:00000000
[    7.512330] [<8002dd8c>] (irq_exit) from [<8006c920>]
(__handle_domain_irq+0x74/0xe4)
[    7.520168]  r4:00000000 r3:00000133
[    7.523800] [<8006c8ac>] (__handle_domain_irq) from [<80008798>]
(gic_handle_irq+0x28/0x68)
[    7.532159]  r10:8073d49c r8:f4000100 r7:80a5ac6c r6:ee0a7f70
r5:0000000d r4:f400010c
[    7.540109] [<80008770>] (gic_handle_irq) from [<80012be4>]
(__irq_svc+0x44/0x5c)
[    7.547604] Exception stack(0xee0a7f70 to 0xee0a7fb8)
[    7.552671] 7f60:                                     00000001
00000001 00000000 80020720
[    7.560862] 7f80: 00000000 80a5a97c 80ab9671 00000001 80ab9671
80a5a9c8 8073d49c ee0a7fc4
[    7.569052] 7fa0: ee0a7f88 ee0a7fb8 800631a4 8000f8e0 20000113 ffffffff
[    7.575674]  r8:80ab9671 r7:ee0a7fa4 r6:ffffffff r5:20000113
r4:8000f8e0 r3:ee076b40
[    7.583544] [<8000f8b8>] (arch_cpu_idle) from [<8005c524>]
(cpu_startup_entry+0x154/0x1b8)
[    7.591829] [<8005c3d0>] (cpu_startup_entry) from [<80014d94>]
(secondary_start_kernel+0x120/0x13c)
[    7.600882]  r7:80ab9c20 r3:ee076b40
[    7.604516] [<80014c74>] (secondary_start_kernel) from [<10008864>]
(0x10008864)
[    7.611921]  r5:00000015 r4:7e08806a
[    7.615577] Unable to handle kernel NULL pointer dereference at
virtual address 00000000
[    7.623703] pgd = 80004000
[    7.626441] [00000000] *pgd=00000000
[    7.630072] Internal error: Oops: 80000005 [#1] SMP ARM
[    7.632780] brcmfmac: _brcmf_set_multicast_list: Setting
BRCMF_C_SET_PROMISC failed, -52
[    7.634175] brcmfmac: _brcmf_set_multicast_list: Setting
BRCMF_C_SET_PROMISC failed, -52
[    7.651495] Sending DHCP requests .
[    7.654993] Modules linked in:
[    7.658060] CPU: 3 PID: 0 Comm: swapper/3 Not tainted
4.0.0-rc3-10351-g94a600d-dirty #6
[    7.666071] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
[    7.672607] task: ee076b40 ti: ee0a6000 task.ti: ee0a6000
[    7.678013] PC is at 0x0
[    7.680559] LR is at call_timer_fn+0x70/0xfc
[    7.684839] pc : [<00000000>]    lr : [<8007aa98>]    psr: 60000113
[    7.684839] sp : ee0a7e38  ip : ee0a7c4c  fp : ee0a7e7c
[    7.696324] r10: 8007aa28  r9 : 00000000  r8 : 00000000
[    7.701557] r7 : 00000100  r6 : 00000000  r5 : 00000001  r4 : ee0a7e48
[    7.708092] r3 : ee076b40  r2 : ee0a7e00  r1 : ee0a7bbc  r0 : 00000000
[    7.714630] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM
Segment kernel
[    7.721946] Control: 10c5387d  Table: 1000404a  DAC: 00000015
[    7.727699] Process swapper/3 (pid: 0, stack limit = 0xee0a6210)

With your patch removed these issues do not happen.

Regards,

Fabio Estevam
diff mbox

Patch

diff --git a/arch/arm/boot/dts/imx6qdl-edm1.dtsi b/arch/arm/boot/dts/imx6qdl-edm1.dtsi
new file mode 100644
index 0000000..6fff536
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-edm1.dtsi
@@ -0,0 +1,230 @@ 
+&iomuxc {
+	pinctrl-names = "default";
+
+	imx6qdl-edm1 {
+
+		pinctrl_audmux: audmuxgrp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
+				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
+				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
+				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
+				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0
+			>;
+		};
+
+		pinctrl_disp0_1: disp0grp-1 {
+			fsl,pins = <
+				MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x10
+				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x10
+				MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x10
+				MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x10
+				MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04		0x10
+				MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x10
+				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x10
+				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x10
+				MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0x10
+				MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0x10
+				MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0x10
+				MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0x10
+				MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0x10
+				MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0x10
+				MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0x10
+				MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0x10
+				MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0x10
+				MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0x10
+				MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0x10
+				MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0x10
+				MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0x10
+				MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0x10
+				MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0x10
+				MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18	0x10
+				MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19	0x10
+				MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20	0x10
+				MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x10
+				MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x10
+				MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x10
+				MX6QDL_PAD_SD4_DAT2__GPIO2_IO10			0x10
+				MX6QDL_PAD_SD4_DAT3__GPIO2_IO11			0x10
+			>;
+		};
+
+		pinctrl_enet: enetgrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
+				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
+				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
+				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
+				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
+				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
+				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
+				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
+				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
+				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
+				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+				MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x180b0
+				MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x000b1
+				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
+			>;
+		};
+
+		pinctrl_flexcan1: flexcan1grp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x1b0b0
+				MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
+				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b0
+			>;
+		};
+
+		pinctrl_flexcan2: flexcan2grp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_7__GPIO1_IO07		0x1b0b0
+				MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x1b0b0
+				MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x1b0b0
+			>;
+		};
+
+		pinctrl_gpmi_nand: gpminandgrp {
+			fsl,pins = <
+				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0x0b0b1
+				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0x0b0b1
+				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0x0b0b1
+				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0x0b000
+				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0x0b0b1
+				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0x0b0b1
+				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0x0b0b1
+				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0x0b0b1
+				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0x0b0b1
+				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0x0b0b1
+				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0x0b0b1
+				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0x0b0b1
+				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0x0b0b1
+				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0x0b0b1
+				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0x0b0b1
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
+				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
+			>;
+		};
+
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
+				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
+			>;
+		};
+
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
+				MX6QDL_PAD_GPIO_16__I2C3_SDA		0x4001b8b1
+			>;
+		};
+
+		pinctrl_pwm3: pwm3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x80000000
+			>;
+		};
+
+		pinctrl_spdif: spdifgrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_RXD0__SPDIF_OUT		0x1b0b0
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+			>;
+		};
+
+		pinctrl_uart1_rtscts: uart1_rtsctsgrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D19__UART1_CTS_B		0x1b0b1
+				MX6QDL_PAD_EIM_D20__UART1_RTS_B		0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
+				MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
+			>;
+		};
+
+
+		pinctrl_uart2_rtscts: uart2_rtsctsgrp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT5__UART2_RTS_B	0x1b0b1
+				MX6QDL_PAD_SD4_DAT6__UART2_CTS_B	0x1b0b1
+			>;
+		};
+
+		pinctrl_usbotg: usbotggrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_9__GPIO1_IO09		0x17059
+				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
+				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x000b0
+			>;
+		};
+
+		pinctrl_usbh1: usbh1grp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x17059
+				MX6QDL_PAD_EIM_D30__GPIO3_IO30		0x1b0b0
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17059
+				MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10059
+				MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17059
+				MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17059
+				MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17059
+				MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17059
+				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x80000000
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
+				MX6QDL_PAD_EIM_DA9__GPIO3_IO09		0x80000000
+			>;
+		};
+	};
+};
+
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
index ef7fa62..39d4239 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
@@ -19,6 +19,7 @@ 
 			fsl,pins = <
 				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0		/* GPIO_0_CLKO */
 				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x80000000	/* uSDHC1 CD */
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8	/* GPIO16 -> AR8035 25MHz */
 				MX6QDL_PAD_EIM_DA9__GPIO3_IO09		0x80000000	/* uSDHC3 CD */
 				MX6QDL_PAD_EIM_EB1__GPIO2_IO29		0x0f0b0		/* WL_REF_ON */
 				MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x0f0b0		/* WL_RST_N */
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi
index 8d893a7..eac30a6 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi
@@ -19,6 +19,7 @@ 
 			fsl,pins = <
 				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0		/* GPIO_0_CLKO */
 				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x80000000	/* uSDHC1 CD */
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8	/* GPIO16 -> AR8035 25MHz */
 				MX6QDL_PAD_EIM_DA9__GPIO3_IO09		0x80000000	/* uSDHC3 CD */
 				MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00	0x0f0b0		/* WIFI_ON (reset, active low) */
 				MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x000b0		/* WL_REG_ON (unused) */
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 5fb0916..4cc9251 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -9,6 +9,8 @@ 
  *
  */
 
+#include "imx6qdl-edm1.dtsi"
+
 / {
 	regulators {
 		compatible = "simple-bus";
@@ -94,64 +96,6 @@ 
 
 	imx6qdl-wandboard {
 
-		pinctrl_audmux: audmuxgrp {
-			fsl,pins = <
-				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
-				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
-				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
-				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
-			>;
-		};
-
-		pinctrl_enet: enetgrp {
-			fsl,pins = <
-				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
-				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
-				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
-				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
-			>;
-		};
-
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D21__I2C1_SCL 		0x4001b8b1
-				MX6QDL_PAD_EIM_D28__I2C1_SDA 		0x4001b8b1
-			>;
-		};
-
-		pinctrl_i2c2: i2c2grp {
-			fsl,pins = <
-				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
-				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
-			>;
-		};
-
-		pinctrl_spdif: spdifgrp {
-			fsl,pins = <
-				MX6QDL_PAD_ENET_RXD0__SPDIF_OUT		0x1b0b0
-			>;
-		};
-
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
-				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
-			>;
-		};
-
 		pinctrl_uart3: uart3grp {
 			fsl,pins = <
 				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
@@ -160,45 +104,6 @@ 
 				MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
 			>;
 		};
-
-		pinctrl_usbotg: usbotggrp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
-			>;
-		};
-
-		pinctrl_usdhc1: usdhc1grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17059
-				MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10059
-				MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17059
-				MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17059
-				MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17059
-				MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17059
-			>;
-		};
-
-		pinctrl_usdhc2: usdhc2grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
-				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
-				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
-				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
-				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
-				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
-			>;
-		};
-
-		pinctrl_usdhc3: usdhc3grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
-				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
-				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
-				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
-				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
-				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
-			>;
-		};
 	};
 };