[v4,2/6] x86: document WC MTRR effects on PAT / non-PAT pages

Commit Message

Luis R. Rodriguez April 29, 2015, 9:44 p.m. UTC

From: "Luis R. Rodriguez" <[e-mail]>

As part of the effort to phase out MTRR use document
write-combining MTRR effects on pages with different
non-PAT page attributes flags and different PAT entry
values. Extend arch_phys_wc_add() documentation to
clarify power of two sizes / boundary requirements as
we phase out mtrr_add() use.

Lastly hint towards ioremap_uc() for corner cases on
device drivers working with devices with mixed regions
where MTRR size requirements would otherwise not
enable write-combining effective memory types.

Cc: Toshi Kani <[e-mail]>
Cc: Jonathan Corbet <[e-mail]>
Cc: Dave Hansen <[e-mail]>
Cc: Andy Lutomirski <[e-mail]>
Cc: Suresh Siddha <[e-mail]>
Cc: Ingo Molnar <[e-mail]>
Cc: Thomas Gleixner <[e-mail]>
Cc: Juergen Gross <[e-mail]>
Cc: Daniel Vetter <[e-mail]>
Cc: Dave Airlie <[e-mail]>
Cc: Antonino Daplas <[e-mail]>
Cc: Jean-Christophe Plagniol-Villard <[e-mail]>
Cc: Tomi Valkeinen <[e-mail]>
Cc: Ville Syrjälä <[e-mail]>
Cc: Mel Gorman <[e-mail]>
Cc: Vlastimil Babka <[e-mail]>
Cc: Borislav Petkov <[e-mail]>
Cc: Davidlohr Bueso <[e-mail]>
Cc: [e-mail]
Cc: [e-mail]
Signed-off-by: Luis R. Rodriguez <[e-mail]>
---
 Documentation/x86/mtrr.txt      | 18 +++++++++++++++---
 Documentation/x86/pat.txt       | 40 +++++++++++++++++++++++++++++++++++++++-
 arch/x86/kernel/cpu/mtrr/main.c |  3 +++
 3 files changed, 57 insertions(+), 4 deletions(-)

Comments

Randy Dunlap April 30, 2015, 10:01 p.m. UTC | #1

On 04/29/15 14:44, Luis R. Rodriguez wrote:
> From: "Luis R. Rodriguez" <[e-mail]>
> 

> ---
>  Documentation/x86/mtrr.txt      | 18 +++++++++++++++---
>  Documentation/x86/pat.txt       | 40 +++++++++++++++++++++++++++++++++++++++-
>  arch/x86/kernel/cpu/mtrr/main.c |  3 +++
>  3 files changed, 57 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/x86/pat.txt b/Documentation/x86/pat.txt
> index cf08c9f..7e183e3 100644
> --- a/Documentation/x86/pat.txt
> +++ b/Documentation/x86/pat.txt
> @@ -102,7 +104,43 @@ wants to export a RAM region, it has to do set_memory_uc() or set_memory_wc()
>  as step 0 above and also track the usage of those pages and use set_memory_wb()
>  before the page is freed to free pool.
>  
> -
> +MTRR effects on PAT / non-PAT systems
> +-------------------------------------
> +
> +The following table provides the effects of using write-combining MTRRs when
> +using ioremap*() calls on x86 for both non-PAT and PAT systems. Ideally
> +mtrr_add() usage will be phased in favor of arch_phys_wc_add() which will
> +be a no-op on PAT enabled systems. The region over which a arch_phys_wc_add()
> +is made should already have be ioremap'd with write-combining page attributes
> +or PAT entries, this can be done by using ioremap_wc() / or respective helpers.
> +Devices which combine areas of IO memory desired to remain uncachable with

I would spell it uncacheable.  In kernel Documentation/, grep uncacheable finds
14 hits vs. 6 hits for uncachable.  No big deal.

> +areas where write-combining is desirable and are restricted by the size
> +requirements of MTRRs should consider splitting up their IO memory space
> +cleanly with ioremap_uc() and ioremap_wc() followed by an arch_phys_wc_add()
> +encompassing both regions. Such use is nevertheless heavily discouraged as
> +the effective memory type is considered implementation defined. This strategy
> +should only be used as last resort on devices with size-contrained regions

                                                      size-constrained

> +where otherwise MTRR write-combining would not be effective.
> +
> +Note that you cannot use set_memory_wc() to override / whitelist IO remapped
> +memory space mapped with ioremap*() calls, set_memory_wc() can only be used
> +on RAM.
> +
> +----------------------------------------------------------------------
> +MTRR Non-PAT   PAT    Linux ioremap value        Effective memory type
> +----------------------------------------------------------------------
> +                                                  Non-PAT |  PAT
> +     PAT
> +     |PCD
> +     ||PWT
> +     |||
> +WC   000      WB      _PAGE_CACHE_MODE_WB            WC   |   WC
> +WC   001      WC      _PAGE_CACHE_MODE_WC            WC*  |   WC
> +WC   010      UC-     _PAGE_CACHE_MODE_UC_MINUS      WC*  |   WC
> +WC   011      UC      _PAGE_CACHE_MODE_UC            UC   |   UC
> +----------------------------------------------------------------------
> +
> +(*) denotes implementation defined and is discouraged
>  
>  Notes:
>  
> diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
> index ea5f363..12abdbe 100644
> --- a/arch/x86/kernel/cpu/mtrr/main.c
> +++ b/arch/x86/kernel/cpu/mtrr/main.c
> @@ -538,6 +538,9 @@ EXPORT_SYMBOL(mtrr_del);
>   * attempts to add a WC MTRR covering size bytes starting at base and
>   * logs an error if this fails.
>   *
> + * The caller should expect to need to provide a power of two size on an

    * The called should provide a power of two size on an equivalent
    * power of two boundary.

> + * equivalent power of two boundary.
> + *
>   * Drivers must store the return value to pass to mtrr_del_wc_if_needed,
>   * but drivers should not try to interpret that return value.
>   */
>

Borislav Petkov May 4, 2015, 12:23 p.m. UTC | #2

On Wed, Apr 29, 2015 at 02:44:07PM -0700, Luis R. Rodriguez wrote:
> From: "Luis R. Rodriguez" <[e-mail]>
> 
> As part of the effort to phase out MTRR use document
> write-combining MTRR effects on pages with different
> non-PAT page attributes flags and different PAT entry
> values. Extend arch_phys_wc_add() documentation to
> clarify power of two sizes / boundary requirements as
> we phase out mtrr_add() use.
> 
> Lastly hint towards ioremap_uc() for corner cases on
> device drivers working with devices with mixed regions
> where MTRR size requirements would otherwise not
> enable write-combining effective memory types.
> 
> Cc: Toshi Kani <[e-mail]>
> Cc: Jonathan Corbet <[e-mail]>
> Cc: Dave Hansen <[e-mail]>
> Cc: Andy Lutomirski <[e-mail]>
> Cc: Suresh Siddha <[e-mail]>
> Cc: Ingo Molnar <[e-mail]>
> Cc: Thomas Gleixner <[e-mail]>
> Cc: Juergen Gross <[e-mail]>
> Cc: Daniel Vetter <[e-mail]>
> Cc: Dave Airlie <[e-mail]>
> Cc: Antonino Daplas <[e-mail]>
> Cc: Jean-Christophe Plagniol-Villard <[e-mail]>
> Cc: Tomi Valkeinen <[e-mail]>
> Cc: Ville Syrjälä <[e-mail]>
> Cc: Mel Gorman <[e-mail]>
> Cc: Vlastimil Babka <[e-mail]>
> Cc: Borislav Petkov <[e-mail]>
> Cc: Davidlohr Bueso <[e-mail]>
> Cc: [e-mail]
> Cc: [e-mail]
> Signed-off-by: Luis R. Rodriguez <[e-mail]>
> ---
>  Documentation/x86/mtrr.txt      | 18 +++++++++++++++---
>  Documentation/x86/pat.txt       | 40 +++++++++++++++++++++++++++++++++++++++-
>  arch/x86/kernel/cpu/mtrr/main.c |  3 +++
>  3 files changed, 57 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/x86/mtrr.txt b/Documentation/x86/mtrr.txt
> index cc071dc..a111a6c 100644
> --- a/Documentation/x86/mtrr.txt
> +++ b/Documentation/x86/mtrr.txt
> @@ -1,7 +1,19 @@
>  MTRR (Memory Type Range Register) control
> -3 Jun 1999
> -Richard Gooch
> -<[e-mail]>
> +
> +Richard Gooch <[e-mail]> - 3 Jun 1999
> +Luis R. Rodriguez <[e-mail]> - April 9, 2015
> +
> +===============================================================================
> +Phasing MTRR use

"Phasing out...".

> +
> +MTRR use is replaced on modern x86 hardware with PAT. Over time the only type
> +of effective MTRR that is expected to be supported will be for write-combining.
> +As MTRR use is phased out device drivers should use arch_phys_wc_add() to make
> +MTRR effective on non-PAT systems while a no-op on PAT enabled systems.
> +
> +For details refer to Documentation/x86/pat.txt.
> +
> +===============================================================================
>  
>    On Intel P6 family processors (Pentium Pro, Pentium II and later)
>    the Memory Type Range Registers (MTRRs) may be used to control
> diff --git a/Documentation/x86/pat.txt b/Documentation/x86/pat.txt
> index cf08c9f..7e183e3 100644
> --- a/Documentation/x86/pat.txt
> +++ b/Documentation/x86/pat.txt
> @@ -34,6 +34,8 @@ ioremap                |    --    |    UC-     |       UC-        |
>                         |          |            |                  |
>  ioremap_cache          |    --    |    WB      |       WB         |
>                         |          |            |                  |
> +ioremap_uc             |    --    |    UC      |       UC         |
> +                       |          |            |                  |
>  ioremap_nocache        |    --    |    UC-     |       UC-        |
>                         |          |            |                  |
>  ioremap_wc             |    --    |    --      |       WC         |
> @@ -102,7 +104,43 @@ wants to export a RAM region, it has to do set_memory_uc() or set_memory_wc()
>  as step 0 above and also track the usage of those pages and use set_memory_wb()
>  before the page is freed to free pool.
>  
> -
> +MTRR effects on PAT / non-PAT systems
> +-------------------------------------
> +
> +The following table provides the effects of using write-combining MTRRs when
> +using ioremap*() calls on x86 for both non-PAT and PAT systems. Ideally
> +mtrr_add() usage will be phased in favor of arch_phys_wc_add() which will

				out

> +be a no-op on PAT enabled systems. The region over which a arch_phys_wc_add()
> +is made should already have be ioremap'd with write-combining page attributes

	 , 		have been ioremapped with WC attributes...

> +or PAT entries, this can be done by using ioremap_wc() / or respective helpers.
> +Devices which combine areas of IO memory desired to remain uncachable with
> +areas where write-combining is desirable and are restricted by the size
> +requirements of MTRRs should consider splitting up their IO memory space
> +cleanly with ioremap_uc() and ioremap_wc() followed by an arch_phys_wc_add()
> +encompassing both regions. Such use is nevertheless heavily discouraged as
> +the effective memory type is considered implementation defined. This strategy
> +should only be used as last resort on devices with size-contrained regions
> +where otherwise MTRR write-combining would not be effective.
> +
> +Note that you cannot use set_memory_wc() to override / whitelist IO remapped
> +memory space mapped with ioremap*() calls, set_memory_wc() can only be used
> +on RAM.
> +
> +----------------------------------------------------------------------
> +MTRR Non-PAT   PAT    Linux ioremap value        Effective memory type
> +----------------------------------------------------------------------
> +                                                  Non-PAT |  PAT
> +     PAT
> +     |PCD
> +     ||PWT
> +     |||
> +WC   000      WB      _PAGE_CACHE_MODE_WB            WC   |   WC
> +WC   001      WC      _PAGE_CACHE_MODE_WC            WC*  |   WC
> +WC   010      UC-     _PAGE_CACHE_MODE_UC_MINUS      WC*  |   WC
> +WC   011      UC      _PAGE_CACHE_MODE_UC            UC   |   UC
> +----------------------------------------------------------------------
> +
> +(*) denotes implementation defined and is discouraged
>  
>  Notes:
>  
> diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
> index ea5f363..12abdbe 100644
> --- a/arch/x86/kernel/cpu/mtrr/main.c
> +++ b/arch/x86/kernel/cpu/mtrr/main.c
> @@ -538,6 +538,9 @@ EXPORT_SYMBOL(mtrr_del);
>   * attempts to add a WC MTRR covering size bytes starting at base and
>   * logs an error if this fails.
>   *
> + * The caller should expect to need to provide a power of two size on an
> + * equivalent power of two boundary.
> + *
>   * Drivers must store the return value to pass to mtrr_del_wc_if_needed,
>   * but drivers should not try to interpret that return value.
>   */
> -- 
> 2.3.2.209.gd67f9d5.dirty
>

Luis Chamberlain May 5, 2015, 12:45 a.m. UTC | #3

On Thu, Apr 30, 2015 at 03:01:12PM -0700, Randy Dunlap wrote:
> On 04/29/15 14:44, Luis R. Rodriguez wrote:
> > From: "Luis R. Rodriguez" <[e-mail]>
> > diff --git a/Documentation/x86/pat.txt b/Documentation/x86/pat.txt
> > index cf08c9f..7e183e3 100644
> > --- a/Documentation/x86/pat.txt
> > +++ b/Documentation/x86/pat.txt
> > @@ -102,7 +104,43 @@ wants to export a RAM region, it has to do set_memory_uc() or set_memory_wc()
> >  as step 0 above and also track the usage of those pages and use set_memory_wb()
> >  before the page is freed to free pool.
> >  
> > -
> > +MTRR effects on PAT / non-PAT systems
> > +-------------------------------------
> > +
> > +The following table provides the effects of using write-combining MTRRs when
> > +using ioremap*() calls on x86 for both non-PAT and PAT systems. Ideally
> > +mtrr_add() usage will be phased in favor of arch_phys_wc_add() which will
> > +be a no-op on PAT enabled systems. The region over which a arch_phys_wc_add()
> > +is made should already have be ioremap'd with write-combining page attributes
> > +or PAT entries, this can be done by using ioremap_wc() / or respective helpers.
> > +Devices which combine areas of IO memory desired to remain uncachable with
> 
> I would spell it uncacheable.  In kernel Documentation/, grep uncacheable finds
> 14 hits vs. 6 hits for uncachable.  No big deal.
> 
> > +areas where write-combining is desirable and are restricted by the size
> > +requirements of MTRRs should consider splitting up their IO memory space
> > +cleanly with ioremap_uc() and ioremap_wc() followed by an arch_phys_wc_add()
> > +encompassing both regions. Such use is nevertheless heavily discouraged as
> > +the effective memory type is considered implementation defined. This strategy
> > +should only be used as last resort on devices with size-contrained regions
> 
>                                                       size-constrained
> 
> > +where otherwise MTRR write-combining would not be effective.
> > +
> > +Note that you cannot use set_memory_wc() to override / whitelist IO remapped
> > +memory space mapped with ioremap*() calls, set_memory_wc() can only be used
> > +on RAM.
> > +
> > +----------------------------------------------------------------------
> > +MTRR Non-PAT   PAT    Linux ioremap value        Effective memory type
> > +----------------------------------------------------------------------
> > +                                                  Non-PAT |  PAT
> > +     PAT
> > +     |PCD
> > +     ||PWT
> > +     |||
> > +WC   000      WB      _PAGE_CACHE_MODE_WB            WC   |   WC
> > +WC   001      WC      _PAGE_CACHE_MODE_WC            WC*  |   WC
> > +WC   010      UC-     _PAGE_CACHE_MODE_UC_MINUS      WC*  |   WC
> > +WC   011      UC      _PAGE_CACHE_MODE_UC            UC   |   UC
> > +----------------------------------------------------------------------
> > +
> > +(*) denotes implementation defined and is discouraged
> >  
> >  Notes:
> >  
> > diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
> > index ea5f363..12abdbe 100644
> > --- a/arch/x86/kernel/cpu/mtrr/main.c
> > +++ b/arch/x86/kernel/cpu/mtrr/main.c
> > @@ -538,6 +538,9 @@ EXPORT_SYMBOL(mtrr_del);
> >   * attempts to add a WC MTRR covering size bytes starting at base and
> >   * logs an error if this fails.
> >   *
> > + * The caller should expect to need to provide a power of two size on an
> 
>     * The called should provide a power of two size on an equivalent
>     * power of two boundary.
> 

Thanks since Boris took this already I'll let him amend unless he wishes for
me to send a new version.

 Luis
--
To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
the body of a message to [e-mail]
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Borislav Petkov May 5, 2015, 7:22 a.m. UTC | #4

On Tue, May 05, 2015 at 02:45:06AM +0200, Luis R. Rodriguez wrote:
> Thanks since Boris took this already I'll let him amend unless he wishes for
> me to send a new version.

Haven't. I'm waiting for v2.

Luis Chamberlain May 5, 2015, 7:31 a.m. UTC | #5

On Thu, Apr 30, 2015 at 03:01:12PM -0700, Randy Dunlap wrote:
> On 04/29/15 14:44, Luis R. Rodriguez wrote:
> > From: "Luis R. Rodriguez" <[e-mail]>
> > 
> 
> > ---
> >  Documentation/x86/mtrr.txt      | 18 +++++++++++++++---
> >  Documentation/x86/pat.txt       | 40 +++++++++++++++++++++++++++++++++++++++-
> >  arch/x86/kernel/cpu/mtrr/main.c |  3 +++
> >  3 files changed, 57 insertions(+), 4 deletions(-)
> > 
> > diff --git a/Documentation/x86/pat.txt b/Documentation/x86/pat.txt
> > index cf08c9f..7e183e3 100644
> > --- a/Documentation/x86/pat.txt
> > +++ b/Documentation/x86/pat.txt
> > @@ -102,7 +104,43 @@ wants to export a RAM region, it has to do set_memory_uc() or set_memory_wc()
> >  as step 0 above and also track the usage of those pages and use set_memory_wb()
> >  before the page is freed to free pool.
> >  
> > -
> > +MTRR effects on PAT / non-PAT systems
> > +-------------------------------------
> > +
> > +The following table provides the effects of using write-combining MTRRs when
> > +using ioremap*() calls on x86 for both non-PAT and PAT systems. Ideally
> > +mtrr_add() usage will be phased in favor of arch_phys_wc_add() which will
> > +be a no-op on PAT enabled systems. The region over which a arch_phys_wc_add()
> > +is made should already have be ioremap'd with write-combining page attributes
> > +or PAT entries, this can be done by using ioremap_wc() / or respective helpers.
> > +Devices which combine areas of IO memory desired to remain uncachable with
> 
> I would spell it uncacheable.  In kernel Documentation/, grep uncacheable finds
> 14 hits vs. 6 hits for uncachable.  No big deal.

Fixed.

> > +areas where write-combining is desirable and are restricted by the size
> > +requirements of MTRRs should consider splitting up their IO memory space
> > +cleanly with ioremap_uc() and ioremap_wc() followed by an arch_phys_wc_add()
> > +encompassing both regions. Such use is nevertheless heavily discouraged as
> > +the effective memory type is considered implementation defined. This strategy
> > +should only be used as last resort on devices with size-contrained regions
> 
>                                                       size-constrained

Fixed.

> > +where otherwise MTRR write-combining would not be effective.
> > +
> > +Note that you cannot use set_memory_wc() to override / whitelist IO remapped
> > +memory space mapped with ioremap*() calls, set_memory_wc() can only be used
> > +on RAM.
> > +
> > +----------------------------------------------------------------------
> > +MTRR Non-PAT   PAT    Linux ioremap value        Effective memory type
> > +----------------------------------------------------------------------
> > +                                                  Non-PAT |  PAT
> > +     PAT
> > +     |PCD
> > +     ||PWT
> > +     |||
> > +WC   000      WB      _PAGE_CACHE_MODE_WB            WC   |   WC
> > +WC   001      WC      _PAGE_CACHE_MODE_WC            WC*  |   WC
> > +WC   010      UC-     _PAGE_CACHE_MODE_UC_MINUS      WC*  |   WC
> > +WC   011      UC      _PAGE_CACHE_MODE_UC            UC   |   UC
> > +----------------------------------------------------------------------
> > +
> > +(*) denotes implementation defined and is discouraged
> >  
> >  Notes:
> >  
> > diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
> > index ea5f363..12abdbe 100644
> > --- a/arch/x86/kernel/cpu/mtrr/main.c
> > +++ b/arch/x86/kernel/cpu/mtrr/main.c
> > @@ -538,6 +538,9 @@ EXPORT_SYMBOL(mtrr_del);
> >   * attempts to add a WC MTRR covering size bytes starting at base and
> >   * logs an error if this fails.
> >   *
> > + * The caller should expect to need to provide a power of two size on an
> 
>     * The called should provide a power of two size on an equivalent
>     * power of two boundary.

Fixed.

 Luis
--
To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
the body of a message to [e-mail]
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Luis Chamberlain May 5, 2015, 7:35 a.m. UTC | #6

On Mon, May 04, 2015 at 02:23:03PM +0200, Borislav Petkov wrote:
> On Wed, Apr 29, 2015 at 02:44:07PM -0700, Luis R. Rodriguez wrote:
> > From: "Luis R. Rodriguez" <[e-mail]>
> > 
> > As part of the effort to phase out MTRR use document
> > write-combining MTRR effects on pages with different
> > non-PAT page attributes flags and different PAT entry
> > values. Extend arch_phys_wc_add() documentation to
> > clarify power of two sizes / boundary requirements as
> > we phase out mtrr_add() use.
> > 
> > Lastly hint towards ioremap_uc() for corner cases on
> > device drivers working with devices with mixed regions
> > where MTRR size requirements would otherwise not
> > enable write-combining effective memory types.
> > 
> > Cc: Toshi Kani <[e-mail]>
> > Cc: Jonathan Corbet <[e-mail]>
> > Cc: Dave Hansen <[e-mail]>
> > Cc: Andy Lutomirski <[e-mail]>
> > Cc: Suresh Siddha <[e-mail]>
> > Cc: Ingo Molnar <[e-mail]>
> > Cc: Thomas Gleixner <[e-mail]>
> > Cc: Juergen Gross <[e-mail]>
> > Cc: Daniel Vetter <[e-mail]>
> > Cc: Dave Airlie <[e-mail]>
> > Cc: Antonino Daplas <[e-mail]>
> > Cc: Jean-Christophe Plagniol-Villard <[e-mail]>
> > Cc: Tomi Valkeinen <[e-mail]>
> > Cc: Ville Syrjälä <[e-mail]>
> > Cc: Mel Gorman <[e-mail]>
> > Cc: Vlastimil Babka <[e-mail]>
> > Cc: Borislav Petkov <[e-mail]>
> > Cc: Davidlohr Bueso <[e-mail]>
> > Cc: [e-mail]
> > Cc: [e-mail]
> > Signed-off-by: Luis R. Rodriguez <[e-mail]>
> > ---
> >  Documentation/x86/mtrr.txt      | 18 +++++++++++++++---
> >  Documentation/x86/pat.txt       | 40 +++++++++++++++++++++++++++++++++++++++-
> >  arch/x86/kernel/cpu/mtrr/main.c |  3 +++
> >  3 files changed, 57 insertions(+), 4 deletions(-)
> > 
> > diff --git a/Documentation/x86/mtrr.txt b/Documentation/x86/mtrr.txt
> > index cc071dc..a111a6c 100644
> > --- a/Documentation/x86/mtrr.txt
> > +++ b/Documentation/x86/mtrr.txt
> > @@ -1,7 +1,19 @@
> >  MTRR (Memory Type Range Register) control
> > -3 Jun 1999
> > -Richard Gooch
> > -<[e-mail]>
> > +
> > +Richard Gooch <[e-mail]> - 3 Jun 1999
> > +Luis R. Rodriguez <[e-mail]> - April 9, 2015
> > +
> > +===============================================================================
> > +Phasing MTRR use
> 
> "Phasing out...".

Fixed all, will send another version.

  Luis
--
To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
the body of a message to [e-mail]
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Luis Chamberlain May 5, 2015, 7:46 a.m. UTC | #7

On Tue, May 05, 2015 at 09:22:14AM +0200, Borislav Petkov wrote:
> On Tue, May 05, 2015 at 02:45:06AM +0200, Luis R. Rodriguez wrote:
> > Thanks since Boris took this already I'll let him amend unless he wishes for
> > me to send a new version.
> 
> Haven't. I'm waiting for v2.

OK thanks, it'll be a v5 actually. I am only resending the documentation patch.

Ville, are you OK with the other atyfb patches that follow up on top of this?
If so since they depend on ioremap_uc() should it go through Boris as he's
taking that in?

 Luis
--
To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
the body of a message to [e-mail]
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Borislav Petkov May 5, 2015, 7:53 a.m. UTC | #8

On Tue, May 05, 2015 at 09:46:34AM +0200, Luis R. Rodriguez wrote:
> If so since they depend on ioremap_uc() should it go through Boris as he's
> taking that in?

Let's slow down a bit first, ok? First let's have all the x86 changes
ready, in and tested. Drivers can convert to them in a following step.

Patch

diff --git a/Documentation/x86/mtrr.txt b/Documentation/x86/mtrr.txt
index cc071dc..a111a6c 100644
--- a/Documentation/x86/mtrr.txt
+++ b/Documentation/x86/mtrr.txt
@@ -1,7 +1,19 @@ 
 MTRR (Memory Type Range Register) control
-3 Jun 1999
-Richard Gooch
-<[e-mail]>
+
+Richard Gooch <[e-mail]> - 3 Jun 1999
+Luis R. Rodriguez <[e-mail]> - April 9, 2015
+
+===============================================================================
+Phasing MTRR use
+
+MTRR use is replaced on modern x86 hardware with PAT. Over time the only type
+of effective MTRR that is expected to be supported will be for write-combining.
+As MTRR use is phased out device drivers should use arch_phys_wc_add() to make
+MTRR effective on non-PAT systems while a no-op on PAT enabled systems.
+
+For details refer to Documentation/x86/pat.txt.
+
+===============================================================================
 
   On Intel P6 family processors (Pentium Pro, Pentium II and later)
   the Memory Type Range Registers (MTRRs) may be used to control
diff --git a/Documentation/x86/pat.txt b/Documentation/x86/pat.txt
index cf08c9f..7e183e3 100644
--- a/Documentation/x86/pat.txt
+++ b/Documentation/x86/pat.txt
@@ -34,6 +34,8 @@  ioremap                |    --    |    UC-     |       UC-        |
                        |          |            |                  |
 ioremap_cache          |    --    |    WB      |       WB         |
                        |          |            |                  |
+ioremap_uc             |    --    |    UC      |       UC         |
+                       |          |            |                  |
 ioremap_nocache        |    --    |    UC-     |       UC-        |
                        |          |            |                  |
 ioremap_wc             |    --    |    --      |       WC         |
@@ -102,7 +104,43 @@  wants to export a RAM region, it has to do set_memory_uc() or set_memory_wc()
 as step 0 above and also track the usage of those pages and use set_memory_wb()
 before the page is freed to free pool.
 
-
+MTRR effects on PAT / non-PAT systems
+-------------------------------------
+
+The following table provides the effects of using write-combining MTRRs when
+using ioremap*() calls on x86 for both non-PAT and PAT systems. Ideally
+mtrr_add() usage will be phased in favor of arch_phys_wc_add() which will
+be a no-op on PAT enabled systems. The region over which a arch_phys_wc_add()
+is made should already have be ioremap'd with write-combining page attributes
+or PAT entries, this can be done by using ioremap_wc() / or respective helpers.
+Devices which combine areas of IO memory desired to remain uncachable with
+areas where write-combining is desirable and are restricted by the size
+requirements of MTRRs should consider splitting up their IO memory space
+cleanly with ioremap_uc() and ioremap_wc() followed by an arch_phys_wc_add()
+encompassing both regions. Such use is nevertheless heavily discouraged as
+the effective memory type is considered implementation defined. This strategy
+should only be used as last resort on devices with size-contrained regions
+where otherwise MTRR write-combining would not be effective.
+
+Note that you cannot use set_memory_wc() to override / whitelist IO remapped
+memory space mapped with ioremap*() calls, set_memory_wc() can only be used
+on RAM.
+
+----------------------------------------------------------------------
+MTRR Non-PAT   PAT    Linux ioremap value        Effective memory type
+----------------------------------------------------------------------
+                                                  Non-PAT |  PAT
+     PAT
+     |PCD
+     ||PWT
+     |||
+WC   000      WB      _PAGE_CACHE_MODE_WB            WC   |   WC
+WC   001      WC      _PAGE_CACHE_MODE_WC            WC*  |   WC
+WC   010      UC-     _PAGE_CACHE_MODE_UC_MINUS      WC*  |   WC
+WC   011      UC      _PAGE_CACHE_MODE_UC            UC   |   UC
+----------------------------------------------------------------------
+
+(*) denotes implementation defined and is discouraged
 
 Notes:
 
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index ea5f363..12abdbe 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -538,6 +538,9 @@  EXPORT_SYMBOL(mtrr_del);
  * attempts to add a WC MTRR covering size bytes starting at base and
  * logs an error if this fails.
  *
+ * The caller should expect to need to provide a power of two size on an
+ * equivalent power of two boundary.
+ *
  * Drivers must store the return value to pass to mtrr_del_wc_if_needed,
  * but drivers should not try to interpret that return value.
  */