| Message ID | 1433159614-437-4-git-send-email-vigneshr@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 06/01/2015 02:53 PM, Vignesh R wrote: > tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux > clock to control ehrpwm tbclk. Care to add TRM reference here? -Tero > > Signed-off-by: Vignesh R <vigneshr@ti.com> > --- > arch/arm/boot/dts/dra7.dtsi | 5 +++++ > arch/arm/boot/dts/dra7xx-clocks.dtsi | 26 ++++++++++++++++++++++++++ > 2 files changed, 31 insertions(+) > > diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi > index f03a091cd076..387c76ca41f9 100644 > --- a/arch/arm/boot/dts/dra7.dtsi > +++ b/arch/arm/boot/dts/dra7.dtsi > @@ -131,6 +131,11 @@ > regulator-max-microvolt = <3000000>; > }; > }; > + > + scm_conf_clocks: clocks { > + #address-cells = <1>; > + #size-cells = <0>; > + }; > }; > > dra7_pmx_core: pinmux@1400 { > diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi > index 3b933f74d000..92452d61cf58 100644 > --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi > +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi > @@ -2136,3 +2136,29 @@ > clocks = <&dpll_usb_ck>; > }; > }; > + > +&scm_conf_clocks { > + ehrpwm0_tbclk: ehrpwm0_tbclk { > + #clock-cells = <0>; > + compatible = "ti,gate-clock"; > + clocks = <&l4_root_clk_div>; > + ti,bit-shift = <20>; > + reg = <0x0558>; > + }; > + > + ehrpwm1_tbclk: ehrpwm1_tbclk { > + #clock-cells = <0>; > + compatible = "ti,gate-clock"; > + clocks = <&l4_root_clk_div>; > + ti,bit-shift = <21>; > + reg = <0x0558>; > + }; > + > + ehrpwm2_tbclk: ehrpwm2_tbclk { > + #clock-cells = <0>; > + compatible = "ti,gate-clock"; > + clocks = <&l4_root_clk_div>; > + ti,bit-shift = <22>; > + reg = <0x0558>; > + }; > +}; > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tuesday 02 June 2015 01:52 PM, Tero Kristo wrote: > On 06/01/2015 02:53 PM, Vignesh R wrote: >> tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux >> clock to control ehrpwm tbclk. > > Care to add TRM reference here? Ok, I will add the following reference. tbclk is derived from SYSCLKOUT. The system clock - SYSCLKOUT is the ePWM functional clock derived from the gateable interface and functional clock of PWMSS. See AM57x TRM SPRUHZ6, October 2014, Section 29.2.2.1, Table 29-19 and the NOTE at the end of the table. > > -Tero > >> >> Signed-off-by: Vignesh R <vigneshr@ti.com> >> --- >> arch/arm/boot/dts/dra7.dtsi | 5 +++++ >> arch/arm/boot/dts/dra7xx-clocks.dtsi | 26 ++++++++++++++++++++++++++ >> 2 files changed, 31 insertions(+) >> >> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi >> index f03a091cd076..387c76ca41f9 100644 >> --- a/arch/arm/boot/dts/dra7.dtsi >> +++ b/arch/arm/boot/dts/dra7.dtsi >> @@ -131,6 +131,11 @@ >> regulator-max-microvolt = <3000000>; >> }; >> }; >> + >> + scm_conf_clocks: clocks { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> }; >> >> dra7_pmx_core: pinmux@1400 { >> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> index 3b933f74d000..92452d61cf58 100644 >> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> @@ -2136,3 +2136,29 @@ >> clocks = <&dpll_usb_ck>; >> }; >> }; >> + >> +&scm_conf_clocks { >> + ehrpwm0_tbclk: ehrpwm0_tbclk { >> + #clock-cells = <0>; >> + compatible = "ti,gate-clock"; >> + clocks = <&l4_root_clk_div>; >> + ti,bit-shift = <20>; >> + reg = <0x0558>; >> + }; >> + >> + ehrpwm1_tbclk: ehrpwm1_tbclk { >> + #clock-cells = <0>; >> + compatible = "ti,gate-clock"; >> + clocks = <&l4_root_clk_div>; >> + ti,bit-shift = <21>; >> + reg = <0x0558>; >> + }; >> + >> + ehrpwm2_tbclk: ehrpwm2_tbclk { >> + #clock-cells = <0>; >> + compatible = "ti,gate-clock"; >> + clocks = <&l4_root_clk_div>; >> + ti,bit-shift = <22>; >> + reg = <0x0558>; >> + }; >> +}; >> > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index f03a091cd076..387c76ca41f9 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -131,6 +131,11 @@ regulator-max-microvolt = <3000000>; }; }; + + scm_conf_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; }; dra7_pmx_core: pinmux@1400 { diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 3b933f74d000..92452d61cf58 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -2136,3 +2136,29 @@ clocks = <&dpll_usb_ck>; }; }; + +&scm_conf_clocks { + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <20>; + reg = <0x0558>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <21>; + reg = <0x0558>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <22>; + reg = <0x0558>; + }; +};
tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux clock to control ehrpwm tbclk. Signed-off-by: Vignesh R <vigneshr@ti.com> --- arch/arm/boot/dts/dra7.dtsi | 5 +++++ arch/arm/boot/dts/dra7xx-clocks.dtsi | 26 ++++++++++++++++++++++++++ 2 files changed, 31 insertions(+)