| Message ID | 1433335514-4156-9-git-send-email-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6530
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 303/303 303/303
SNB -1 315/315 314/315
IVB 343/343 343/343
BYT 287/287 287/287
BDW 321/321 321/321
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*SNB igt@pm_rpm@dpms-mode-unset-non-lpsp PASS(1) DMESG_WARN(1)
(dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#assert_device_not_suspended[i915]()@WARNING:.* at .* assert_device_not_suspended+0x
Note: You need to pay more attention to line start with '*'
On Wed, 03 Jun 2015, Mika Kahola <mika.kahola@intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Implement support for changing the cdclk frequency during runtime on > HSW. VLV/CHV already have support for this, so we can follow their > example for the most part. Only the actual hardware programming differs, > the rest is pretty much the same. I'm chickening out of this one. Thanks to the new patch ordering we can return to it later if needed. BR, Jani. > > The pipe pixel rate stuff is handled a bit differently for now due to > the difference in pch vs. gmch pfit handling. Eventually we should unify > that part to eliminate what is essentially duplicated code. > > v2: Grab rps.hw_lock around sandybridge_pcode_write() > v3: Rebase due to power well vs. .global_resources() reordering > v4: Rebased to the latest > v5: Reformatting 'haswell_modeset_global_pipes' function to > support atomic state > v6: Shuffling the patch order so the Broadwell CD clock patch > can be applied before this Haswell CD clock patch > v7: Fix for patch style problems > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > > Author: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 2 + > drivers/gpu/drm/i915/intel_display.c | 137 ++++++++++++++++++++++++++++++++++- > 2 files changed, 136 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0f72c0e..418d149 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6705,6 +6705,7 @@ enum skl_disp_power_wells { > #define GEN6_PCODE_READ_RC6VIDS 0x5 > #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) > #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) > +#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 > #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 > #define GEN9_PCODE_READ_MEM_LATENCY 0x6 > #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF > @@ -7167,6 +7168,7 @@ enum skl_disp_power_wells { > #define LCPLL_PLL_LOCK (1<<30) > #define LCPLL_CLK_FREQ_MASK (3<<26) > #define LCPLL_CLK_FREQ_450 (0<<26) > +#define LCPLL_CLK_FREQ_ALT_HSW (1<<26) /* 337.5 (ULX) or 540 */ > #define LCPLL_CLK_FREQ_54O_BDW (1<<26) > #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) > #define LCPLL_CLK_FREQ_675_BDW (3<<26) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index b1e2069..4b9907d 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5751,7 +5751,16 @@ static void intel_update_max_cdclk(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (IS_BROADWELL(dev)) { > + if (IS_HASWELL(dev)) { > + if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) > + dev_priv->max_cdclk_freq = 450000; > + else if (IS_HSW_ULX(dev)) > + dev_priv->max_cdclk_freq = 337500; > + else if (IS_HSW_ULT(dev)) > + dev_priv->max_cdclk_freq = 450000; > + else > + dev_priv->max_cdclk_freq = 540000; > + } else if (IS_BROADWELL(dev)) { > /* > * FIXME with extra cooling we can allow > * 540 MHz for ULX and 675 Mhz for ULT. > @@ -9755,6 +9764,80 @@ static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv, > return cdclk; > } > > +static void haswell_set_cdclk(struct drm_device *dev, int cdclk) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + uint32_t val; > + > + if (WARN((I915_READ(LCPLL_CTL) & > + (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | > + LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | > + LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | > + LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, > + "trying to change cdclk frequency with cdclk not enabled\n")) > + return; > + > + val = I915_READ(LCPLL_CTL); > + val &= ~LCPLL_CLK_FREQ_MASK; > + > + switch (cdclk) { > + case 450000: > + val |= LCPLL_CLK_FREQ_450; > + break; > + case 337500: > + case 540000: > + val |= LCPLL_CLK_FREQ_ALT_HSW; > + break; > + default: > + WARN(1, "invalid cdclk frequency\n"); > + return; > + } > + > + I915_WRITE(LCPLL_CTL, val); > + > + if (IS_HSW_ULX(dev)) { > + mutex_lock(&dev_priv->rps.hw_lock); > + sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, > + cdclk == 337500); > + mutex_unlock(&dev_priv->rps.hw_lock); > + } > + > + intel_update_cdclk(dev); > + > + WARN(cdclk != dev_priv->cdclk_freq, > + "cdclk requested %d kHz but got %d kHz\n", > + cdclk, dev_priv->cdclk_freq); > +} > + > +static int haswell_calc_cdclk(struct drm_i915_private *dev_priv, > + int max_pixel_rate) > +{ > + int cdclk; > + > + /* > + * FIXME should also account for plane ratio > + * once 64bpp pixel formats are supported. > + */ > + if (max_pixel_rate > 450000) > + cdclk = 540000; > + else if (max_pixel_rate > 337500 || !IS_HSW_ULX(dev_priv)) > + cdclk = 450000; > + else > + cdclk = 337500; > + > + /* > + * FIXME move the cdclk caclulation to > + * compute_config() so we can fail gracegully. > + */ > + if (cdclk > dev_priv->max_cdclk_freq) { > + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", > + cdclk, dev_priv->max_cdclk_freq); > + cdclk = dev_priv->max_cdclk_freq; > + } > + > + return cdclk; > +} > + > static int broadwell_modeset_global_pipes(struct drm_atomic_state *state) > { > struct drm_i915_private *dev_priv = to_i915(state->dev); > @@ -9797,6 +9880,49 @@ static void broadwell_modeset_global_resources(struct drm_atomic_state *state) > broadwell_set_cdclk(dev, req_cdclk); > } > > +static int haswell_modeset_global_pipes(struct drm_atomic_state *state) > +{ > + struct drm_i915_private *dev_priv = to_i915(state->dev); > + struct drm_crtc *crtc; > + struct drm_crtc_state *crtc_state; > + int max_pixclk = ilk_max_pixel_rate(dev_priv); > + int cdclk, i; > + > + cdclk = haswell_calc_cdclk(dev_priv, max_pixclk); > + > + if (cdclk == dev_priv->cdclk_freq) > + return 0; > + > + /* add all active pipes to the state */ > + for_each_crtc(state->dev, crtc) { > + if (!crtc->state->enable) > + continue; > + > + crtc_state = drm_atomic_get_crtc_state(state, crtc); > + if (IS_ERR(crtc_state)) > + return PTR_ERR(crtc_state); > + } > + > + /* disable/enable all currently active pipes while we change cdclk */ > + for_each_crtc_in_state(state, crtc, crtc_state, i) > + if (crtc_state->enable) > + crtc_state->mode_changed = true; > + > + return 0; > +} > + > +static void haswell_modeset_global_resources(struct drm_atomic_state *state) > +{ > + struct drm_device *dev = state->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + int max_pixel_rate = ilk_max_pixel_rate(dev_priv); > + int req_cdclk = haswell_calc_cdclk(dev_priv, max_pixel_rate); > + > + if (req_cdclk != dev_priv->cdclk_freq) { > + haswell_set_cdclk(dev, req_cdclk); > + } > +} > + > static int haswell_crtc_compute_clock(struct intel_crtc *crtc, > struct intel_crtc_state *crtc_state) > { > @@ -12977,11 +13103,13 @@ static int __intel_set_mode_checks(struct drm_atomic_state *state) > * mode set on this crtc. For other crtcs we need to use the > * adjusted_mode bits in the crtc directly. > */ > - if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) { > + if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev) || IS_HASWELL(dev)) { > if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) > ret = valleyview_modeset_global_pipes(state); > - else > + else if (IS_BROADWELL(dev)) > ret = broadwell_modeset_global_pipes(state); > + else > + ret = haswell_modeset_global_pipes(state); > > if (ret) > return ret; > @@ -14873,6 +15001,9 @@ static void intel_init_display(struct drm_device *dev) > if (IS_BROADWELL(dev)) > dev_priv->display.modeset_global_resources = > broadwell_modeset_global_resources; > + else > + dev_priv->display.modeset_global_resources = > + haswell_modeset_global_resources; > } else if (IS_VALLEYVIEW(dev)) { > dev_priv->display.modeset_global_resources = > valleyview_modeset_global_resources; > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0f72c0e..418d149 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6705,6 +6705,7 @@ enum skl_disp_power_wells { #define GEN6_PCODE_READ_RC6VIDS 0x5 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) +#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF @@ -7167,6 +7168,7 @@ enum skl_disp_power_wells { #define LCPLL_PLL_LOCK (1<<30) #define LCPLL_CLK_FREQ_MASK (3<<26) #define LCPLL_CLK_FREQ_450 (0<<26) +#define LCPLL_CLK_FREQ_ALT_HSW (1<<26) /* 337.5 (ULX) or 540 */ #define LCPLL_CLK_FREQ_54O_BDW (1<<26) #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) #define LCPLL_CLK_FREQ_675_BDW (3<<26) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b1e2069..4b9907d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5751,7 +5751,16 @@ static void intel_update_max_cdclk(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (IS_BROADWELL(dev)) { + if (IS_HASWELL(dev)) { + if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) + dev_priv->max_cdclk_freq = 450000; + else if (IS_HSW_ULX(dev)) + dev_priv->max_cdclk_freq = 337500; + else if (IS_HSW_ULT(dev)) + dev_priv->max_cdclk_freq = 450000; + else + dev_priv->max_cdclk_freq = 540000; + } else if (IS_BROADWELL(dev)) { /* * FIXME with extra cooling we can allow * 540 MHz for ULX and 675 Mhz for ULT. @@ -9755,6 +9764,80 @@ static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv, return cdclk; } +static void haswell_set_cdclk(struct drm_device *dev, int cdclk) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t val; + + if (WARN((I915_READ(LCPLL_CTL) & + (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | + LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | + LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | + LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, + "trying to change cdclk frequency with cdclk not enabled\n")) + return; + + val = I915_READ(LCPLL_CTL); + val &= ~LCPLL_CLK_FREQ_MASK; + + switch (cdclk) { + case 450000: + val |= LCPLL_CLK_FREQ_450; + break; + case 337500: + case 540000: + val |= LCPLL_CLK_FREQ_ALT_HSW; + break; + default: + WARN(1, "invalid cdclk frequency\n"); + return; + } + + I915_WRITE(LCPLL_CTL, val); + + if (IS_HSW_ULX(dev)) { + mutex_lock(&dev_priv->rps.hw_lock); + sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, + cdclk == 337500); + mutex_unlock(&dev_priv->rps.hw_lock); + } + + intel_update_cdclk(dev); + + WARN(cdclk != dev_priv->cdclk_freq, + "cdclk requested %d kHz but got %d kHz\n", + cdclk, dev_priv->cdclk_freq); +} + +static int haswell_calc_cdclk(struct drm_i915_private *dev_priv, + int max_pixel_rate) +{ + int cdclk; + + /* + * FIXME should also account for plane ratio + * once 64bpp pixel formats are supported. + */ + if (max_pixel_rate > 450000) + cdclk = 540000; + else if (max_pixel_rate > 337500 || !IS_HSW_ULX(dev_priv)) + cdclk = 450000; + else + cdclk = 337500; + + /* + * FIXME move the cdclk caclulation to + * compute_config() so we can fail gracegully. + */ + if (cdclk > dev_priv->max_cdclk_freq) { + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", + cdclk, dev_priv->max_cdclk_freq); + cdclk = dev_priv->max_cdclk_freq; + } + + return cdclk; +} + static int broadwell_modeset_global_pipes(struct drm_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->dev); @@ -9797,6 +9880,49 @@ static void broadwell_modeset_global_resources(struct drm_atomic_state *state) broadwell_set_cdclk(dev, req_cdclk); } +static int haswell_modeset_global_pipes(struct drm_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->dev); + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; + int max_pixclk = ilk_max_pixel_rate(dev_priv); + int cdclk, i; + + cdclk = haswell_calc_cdclk(dev_priv, max_pixclk); + + if (cdclk == dev_priv->cdclk_freq) + return 0; + + /* add all active pipes to the state */ + for_each_crtc(state->dev, crtc) { + if (!crtc->state->enable) + continue; + + crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + } + + /* disable/enable all currently active pipes while we change cdclk */ + for_each_crtc_in_state(state, crtc, crtc_state, i) + if (crtc_state->enable) + crtc_state->mode_changed = true; + + return 0; +} + +static void haswell_modeset_global_resources(struct drm_atomic_state *state) +{ + struct drm_device *dev = state->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + int max_pixel_rate = ilk_max_pixel_rate(dev_priv); + int req_cdclk = haswell_calc_cdclk(dev_priv, max_pixel_rate); + + if (req_cdclk != dev_priv->cdclk_freq) { + haswell_set_cdclk(dev, req_cdclk); + } +} + static int haswell_crtc_compute_clock(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state) { @@ -12977,11 +13103,13 @@ static int __intel_set_mode_checks(struct drm_atomic_state *state) * mode set on this crtc. For other crtcs we need to use the * adjusted_mode bits in the crtc directly. */ - if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) { + if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev) || IS_HASWELL(dev)) { if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) ret = valleyview_modeset_global_pipes(state); - else + else if (IS_BROADWELL(dev)) ret = broadwell_modeset_global_pipes(state); + else + ret = haswell_modeset_global_pipes(state); if (ret) return ret; @@ -14873,6 +15001,9 @@ static void intel_init_display(struct drm_device *dev) if (IS_BROADWELL(dev)) dev_priv->display.modeset_global_resources = broadwell_modeset_global_resources; + else + dev_priv->display.modeset_global_resources = + haswell_modeset_global_resources; } else if (IS_VALLEYVIEW(dev)) { dev_priv->display.modeset_global_resources = valleyview_modeset_global_resources;