| Message ID | 1433509653-15142-1-git-send-email-ranjit.waghmode@xilinx.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, 2015-06-05 at 06:37PM +0530, Ranjit Waghmode wrote: > Add bindings documentation for GQSPI controller driver used by > Zynq Ultrascale+ MPSoC > > Signed-off-by: Ranjit Waghmode <ranjit.waghmode@xilinx.com> > --- > No changes in v2 > --- > .../devicetree/bindings/spi/spi-zynqmp-qspi.txt | 26 ++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > create mode 100644 Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt > > diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt > new file mode 100644 > index 0000000..cec6330 > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt > @@ -0,0 +1,26 @@ > +Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings > +------------------------------------------------------------------- > + > +Required properties: > +- compatible : Should be "xlnx,zynqmp-qspi-1.0". > +- reg : Physical base address and size of GQSPI registers map. > +- interrupts : Property with a value describing the interrupt > + number. > +- interrupt-parent : Must be core interrupt controller. > +- clock-names : List of input clock names - "ref_clk", "pclk" > + (See clock bindings for details). > +- clocks : Clock phandles (see clock bindings for details). > + > +Optional properties: > +- num-cs : Number of chip selects used. > + > +Example: > + qspi: spi@ff0f0000 { > + compatible = "xlnx,zynqmp-qspi-1.0"; > + clock-names = "ref_clk", "pclk"; > + clocks = <&misc_clk &misc_clk>; > + interrupts = <0 15 4>; > + interrupt-parent = <&gic>; > + num-cs = <1>; > + reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>; Please make this reg = <0x0 0xff0f0000 0x1000>, <0x0 0xc0000000 0x8000000>; Sören -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Soren, > > .../devicetree/bindings/spi/spi-zynqmp-qspi.txt | 26 > ++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt > > > > diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt > > b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt > > new file mode 100644 > > index 0000000..cec6330 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt > > @@ -0,0 +1,26 @@ > > +Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings > > +------------------------------------------------------------------- > > + > > +Required properties: > > +- compatible : Should be "xlnx,zynqmp-qspi-1.0". > > +- reg : Physical base address and size of GQSPI registers map. > > +- interrupts : Property with a value describing the interrupt > > + number. > > +- interrupt-parent : Must be core interrupt controller. > > +- clock-names : List of input clock names - "ref_clk", "pclk" > > + (See clock bindings for details). > > +- clocks : Clock phandles (see clock bindings for details). > > + > > +Optional properties: > > +- num-cs : Number of chip selects used. > > + > > +Example: > > + qspi: spi@ff0f0000 { > > + compatible = "xlnx,zynqmp-qspi-1.0"; > > + clock-names = "ref_clk", "pclk"; > > + clocks = <&misc_clk &misc_clk>; > > + interrupts = <0 15 4>; > > + interrupt-parent = <&gic>; > > + num-cs = <1>; > > + reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>; > > Please make this > reg = <0x0 0xff0f0000 0x1000>, <0x0 0xc0000000 0x8000000>; > Sorry for this miss. Will update in next version. Regards, Ranjit Waghmode, ranjitw@xilinx.com This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt new file mode 100644 index 0000000..cec6330 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt @@ -0,0 +1,26 @@ +Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings +------------------------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,zynqmp-qspi-1.0". +- reg : Physical base address and size of GQSPI registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupt-parent : Must be core interrupt controller. +- clock-names : List of input clock names - "ref_clk", "pclk" + (See clock bindings for details). +- clocks : Clock phandles (see clock bindings for details). + +Optional properties: +- num-cs : Number of chip selects used. + +Example: + qspi: spi@ff0f0000 { + compatible = "xlnx,zynqmp-qspi-1.0"; + clock-names = "ref_clk", "pclk"; + clocks = <&misc_clk &misc_clk>; + interrupts = <0 15 4>; + interrupt-parent = <&gic>; + num-cs = <1>; + reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>; + };
Add bindings documentation for GQSPI controller driver used by Zynq Ultrascale+ MPSoC Signed-off-by: Ranjit Waghmode <ranjit.waghmode@xilinx.com> --- No changes in v2 --- .../devicetree/bindings/spi/spi-zynqmp-qspi.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt -- 2.1.2 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html