| Message ID | 1435075417-28708-1-git-send-email-fabio.estevam@freescale.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Am Dienstag, den 23.06.2015, 13:03 -0300 schrieb Fabio Estevam: > Currently it is not possible to have HDMI and LVDS working simultaneously, > because both ports try to use PLL5. > > Move the LVDS to PLL3_USB_OTG, so that HDMI and LVDS can be driven from > independent sources. > > With this change the LDB pixel clock goes to 68.57 MHz, which is still > within the valid range for the HSD100PXN1 LVDS panel. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Please remember that on i.MX6QDL in general we can't change the LDB clock parent without risking a breakdown in the divider: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/313618.html http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/313619.html http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/313620.html Has there been an erratum for this issue yet? best regards Philipp
Hi Phillip, On Tue, Jun 23, 2015 at 1:23 PM, Philipp Zabel <p.zabel@pengutronix.de> wrote: > Please remember that on i.MX6QDL in general we can't change the LDB > clock parent without risking a breakdown in the divider: > > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/313618.html > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/313619.html > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/313620.html Yes, I am aware of this issue. However this patch does not make things worse with this respect. Instead of changing the LDB parent to PLL5 this patch changes to PLL3 instead. > Has there been an erratum for this issue yet? I was told we should see it online within a few weeks. Hopefully we would be able to revisit your patch series after this happens. Regards, Fabio Estevam
Hi Fabio, Am Dienstag, den 23.06.2015, 13:32 -0300 schrieb Fabio Estevam: > Hi Phillip, > > On Tue, Jun 23, 2015 at 1:23 PM, Philipp Zabel <p.zabel@pengutronix.de> wrote: > > > Please remember that on i.MX6QDL in general we can't change the LDB > > clock parent without risking a breakdown in the divider: > > > > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/313618.html > > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/313619.html > > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/313620.html > > Yes, I am aware of this issue. > > However this patch does not make things worse with this respect. > Instead of changing the LDB parent to PLL5 this patch changes to PLL3 > instead. If we later make the ldb_di_sel muxes read-only (patch 2 above), this change will not work anymore. If my (version of your initial) patch 3 gets accepted, the assigned-clock-parents property will keep working for ldb_di_sel only if it is placed in the clks device tree node. > > Has there been an erratum for this issue yet? > > I was told we should see it online within a few weeks. Hopefully we > would be able to revisit your patch series after this happens. Good news, thank you. regards Philipp
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index a626e6d..dd1bedb 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -494,6 +494,10 @@ }; &ldb { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; status = "okay"; lvds-channel@1 {
Currently it is not possible to have HDMI and LVDS working simultaneously, because both ports try to use PLL5. Move the LVDS to PLL3_USB_OTG, so that HDMI and LVDS can be driven from independent sources. With this change the LDB pixel clock goes to 68.57 MHz, which is still within the valid range for the HSD100PXN1 LVDS panel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 4 ++++ 1 file changed, 4 insertions(+)