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[6/6] drm/i915: Added BXT check in HAS_CORE_RING_FREQ macro

Message ID 1435569624-28693-7-git-send-email-akash.goel@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

akash.goel@intel.com June 29, 2015, 9:20 a.m. UTC 
From: Akash Goel <akash.goel@intel.com>

Updated the HAS_CORE_RING_FREQ macro to add the broxton check,
so as to disallow the programming & read of ring frequency
table for it.

Issue: VIZ-5144
Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Shuang He June 29, 2015, 8:28 p.m. UTC | #1 
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6658
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                                  302/302              302/302
SNB                                  312/316              312/316
IVB                                  343/343              343/343
BYT                 -4              287/287              283/287
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*BYT  igt@gem_partial_pwrite_pread@reads      PASS(1)      FAIL(1)
*BYT  igt@gem_partial_pwrite_pread@reads-display      PASS(1)      FAIL(1)
*BYT  igt@gem_partial_pwrite_pread@reads-uncached      PASS(1)      FAIL(1)
*BYT  igt@gem_tiled_partial_pwrite_pread@reads      PASS(1)      FAIL(1)
Note: You need to pay more attention to line start with '*'
Rodrigo Vivi July 9, 2015, 10:02 p.m. UTC | #2 
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


On Mon, Jun 29, 2015 at 1:28 PM <shuang.he@intel.com> wrote:

> Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
> shuang.he@intel.com)
> Task id: 6658
>
> -------------------------------------Summary-------------------------------------
> Platform          Delta          drm-intel-nightly          Series Applied
> ILK                                  302/302              302/302
> SNB                                  312/316              312/316
> IVB                                  343/343              343/343
> BYT                 -4              287/287              283/287
>
> -------------------------------------Detailed-------------------------------------
> Platform  Test                                drm-intel-nightly
> Series Applied
> *BYT  igt@gem_partial_pwrite_pread@reads      PASS(1)      FAIL(1)
> *BYT  igt@gem_partial_pwrite_pread@reads-display      PASS(1)      FAIL(1)
> *BYT  igt@gem_partial_pwrite_pread@reads-uncached      PASS(1)
> FAIL(1)
> *BYT  igt@gem_tiled_partial_pwrite_pread@reads      PASS(1)      FAIL(1)
> Note: You need to pay more attention to line start with '*'
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7b6aa71..6f927b6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2521,7 +2521,7 @@  struct drm_i915_cmd_table {
 #define HAS_CSR(dev)	(IS_SKYLAKE(dev))
 
 #define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
-				 !IS_VALLEYVIEW(dev))
+				 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00