| Message ID | 1435594615-9570-2-git-send-email-fabio.estevam@freescale.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Fabio, All, On Mon, Jun 29, 2015 at 6:16 PM, Fabio Estevam <fabio.estevam@freescale.com> wrote: > Currently it is not possible to have HDMI and LVDS working simultaneously, > because both ports try to use PLL5. > > Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be > driven from independent sources. > > With this change the LDB pixel clock goes to 68.57 MHz, which is still > within the valid range for the HSD100PXN1 LVDS panel. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- > arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi > index 3af16df..1cba390 100644 > --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi > +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi > @@ -149,6 +149,13 @@ > status = "okay"; > }; > > +&clks { > + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, > + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; > + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, > + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; > +}; > + > &ecspi1 { > fsl,spi-num-chipselects = <1>; > cs-gpios = <&gpio3 19 0>; > -- > 1.9.1 > Tested using linux-next 20150629 on Nitrogen6x with either Hannstar 7" or 10" + HDMI monitor. This patch relies on previous clk-imx6q patch from Fabio: https://patchwork.kernel.org/patch/6682561/ Tested-by: Gary Bisson <gary.bisson@boundarydevices.com> Regards, Gary
Am Montag, den 29.06.2015, 13:16 -0300 schrieb Fabio Estevam: > Currently it is not possible to have HDMI and LVDS working simultaneously, > because both ports try to use PLL5. > > Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be > driven from independent sources. > > With this change the LDB pixel clock goes to 68.57 MHz, which is still > within the valid range for the HSD100PXN1 LVDS panel. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- > arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi > index 3af16df..1cba390 100644 > --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi > +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi > @@ -149,6 +149,13 @@ > status = "okay"; > }; > > +&clks { > + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, > + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; > + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, > + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; > +}; Tested-by: Philipp Zabel <p.zabel@pengutronix.de> with a HannStar HSD070PWW1 7" 1280x800 panel (results in 58.93 Hz vrefresh with the default timings). regards Philipp
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 3af16df..1cba390 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -149,6 +149,13 @@ status = "okay"; }; +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>;
Currently it is not possible to have HDMI and LVDS working simultaneously, because both ports try to use PLL5. Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be driven from independent sources. With this change the LDB pixel clock goes to 68.57 MHz, which is still within the valid range for the HSD100PXN1 LVDS panel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)