| Message ID | 1435923357-3821-7-git-send-email-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jul 03, 2015 at 02:35:54PM +0300, Mika Kahola wrote: > It is possible the we request to have a mode that has > higher pixel clock than our HW can support. This patch > checks if requested pixel clock is lower than the one > supported by the HW. The requested mode is discarded > if we cannot support the requested pixel clock. > > This patch applies to DSI. > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index 98998e9..1cf35b8 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -635,15 +635,39 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, > pipe_config->port_clock = pclk; > } > > +static int > +intel_dsi_max_pixclk(struct intel_dsi *intel_dsi) > +{ > + struct drm_device *dev = intel_dsi->base.base.dev; > + struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_crtc *intel_crtc = to_intel_crtc(intel_dsi->base.base.crtc); > + > + if (IS_CHERRYVIEW(dev)) > + return DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 95); > + else if (IS_VALLEYVIEW(dev)) > + return DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 90); > + else if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled) > + return DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 95); > + else > + return dev_priv->max_cdclk_freq; > +} > + > static enum drm_mode_status > intel_dsi_mode_valid(struct drm_connector *connector, > struct drm_display_mode *mode) > { > struct intel_connector *intel_connector = to_intel_connector(connector); > struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; > + struct intel_encoder *intel_encoder = intel_connector->encoder; > + struct drm_encoder *encoder = &intel_encoder->base; > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > + int max_pixclk = intel_dsi_max_pixclk(intel_dsi); > > DRM_DEBUG_KMS("\n"); > > + if (mode->clock > max_pixclk) > + return MODE_PANEL; return MODE_CLOCK_HIGH; -Chris
On Fri, 2015-07-03 at 13:38 +0100, Chris Wilson wrote: > On Fri, Jul 03, 2015 at 02:35:54PM +0300, Mika Kahola wrote: > > It is possible the we request to have a mode that has > > higher pixel clock than our HW can support. This patch > > checks if requested pixel clock is lower than the one > > supported by the HW. The requested mode is discarded > > if we cannot support the requested pixel clock. > > > > This patch applies to DSI. > > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > > --- > > drivers/gpu/drm/i915/intel_dsi.c | 24 ++++++++++++++++++++++++ > > 1 file changed, 24 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > > index 98998e9..1cf35b8 100644 > > --- a/drivers/gpu/drm/i915/intel_dsi.c > > +++ b/drivers/gpu/drm/i915/intel_dsi.c > > @@ -635,15 +635,39 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, > > pipe_config->port_clock = pclk; > > } > > > > +static int > > +intel_dsi_max_pixclk(struct intel_dsi *intel_dsi) > > +{ > > + struct drm_device *dev = intel_dsi->base.base.dev; > > + struct drm_i915_private *dev_priv = to_i915(dev); > > + struct intel_crtc *intel_crtc = to_intel_crtc(intel_dsi->base.base.crtc); > > + > > + if (IS_CHERRYVIEW(dev)) > > + return DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 95); > > + else if (IS_VALLEYVIEW(dev)) > > + return DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 90); > > + else if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled) > > + return DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 95); > > + else > > + return dev_priv->max_cdclk_freq; > > +} > > + > > static enum drm_mode_status > > intel_dsi_mode_valid(struct drm_connector *connector, > > struct drm_display_mode *mode) > > { > > struct intel_connector *intel_connector = to_intel_connector(connector); > > struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; > > + struct intel_encoder *intel_encoder = intel_connector->encoder; > > + struct drm_encoder *encoder = &intel_encoder->base; > > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > > + int max_pixclk = intel_dsi_max_pixclk(intel_dsi); > > > > DRM_DEBUG_KMS("\n"); > > > > + if (mode->clock > max_pixclk) > > + return MODE_PANEL; > > return MODE_CLOCK_HIGH; > -Chris > Thanks Chris! I'll change this one. Cheers, Mika
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 98998e9..1cf35b8 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -635,15 +635,39 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, pipe_config->port_clock = pclk; } +static int +intel_dsi_max_pixclk(struct intel_dsi *intel_dsi) +{ + struct drm_device *dev = intel_dsi->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *intel_crtc = to_intel_crtc(intel_dsi->base.base.crtc); + + if (IS_CHERRYVIEW(dev)) + return DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 95); + else if (IS_VALLEYVIEW(dev)) + return DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 90); + else if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled) + return DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 95); + else + return dev_priv->max_cdclk_freq; +} + static enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { struct intel_connector *intel_connector = to_intel_connector(connector); struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; + struct intel_encoder *intel_encoder = intel_connector->encoder; + struct drm_encoder *encoder = &intel_encoder->base; + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); + int max_pixclk = intel_dsi_max_pixclk(intel_dsi); DRM_DEBUG_KMS("\n"); + if (mode->clock > max_pixclk) + return MODE_PANEL; + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); return MODE_NO_DBLESCAN;
It is possible the we request to have a mode that has higher pixel clock than our HW can support. This patch checks if requested pixel clock is lower than the one supported by the HW. The requested mode is discarded if we cannot support the requested pixel clock. This patch applies to DSI. Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- drivers/gpu/drm/i915/intel_dsi.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)