| Message ID | 1435569624-28693-2-git-send-email-akash.goel@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
I don't have the spec so I can just assume it was like previous platforms. For me this 50MHz x 16.6MHz is still confusing (like clamp in 50 than convert to 16.6)... but nevermind... apparently we are not mixing stuff in the sense we compare values in different scales... Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> On Mon, Jun 29, 2015 at 2:11 AM <akash.goel@intel.com> wrote: > From: Akash Goel <akash.goel@intel.com> > > Read the efficient frequency (aka RPe) value through the the mailbox > command (0x1A) from the pcode, as done on Haswell and Broadwell. > The turbo minimum frequency softlimit is not revised as per the > efficient frequency value. > > v2: Replaced the conditional expression operator with 'if' statement (Tom) > v3: Corrected the derivation of efficient frequency & shifted the > GEN9_FREQ_SCALER multiplications downwards (Ville) > > Issue: VIZ-5143 > Signed-off-by: Akash Goel <akash.goel@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++-------- > 1 file changed, 11 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c > index 32ff034..8185a23 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4295,18 +4295,11 @@ static void gen6_init_rps_frequencies(struct > drm_device *dev) > dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; > dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; > dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; > - if (IS_SKYLAKE(dev)) { > - /* Store the frequency values in 16.66 MHZ units, which is > - the natural hardware unit for SKL */ > - dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; > - dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; > - dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; > - } > /* hw_max = RP0 until we check for overclocking */ > dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; > > dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; > - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { > + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { > ret = sandybridge_pcode_read(dev_priv, > > HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, > &ddcc_status); > @@ -4318,6 +4311,16 @@ static void gen6_init_rps_frequencies(struct > drm_device *dev) > dev_priv->rps.max_freq); > } > > + if (IS_SKYLAKE(dev)) { > + /* Store the frequency values in 16.66 MHZ units, which is > + the natural hardware unit for SKL */ > + dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; > + dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; > + dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; > + dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; > + dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; > + } > + > dev_priv->rps.idle_freq = dev_priv->rps.min_freq; > > /* Preserve min/max settings in case of re-init */ > -- > 1.9.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 32ff034..8185a23 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4295,18 +4295,11 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; - if (IS_SKYLAKE(dev)) { - /* Store the frequency values in 16.66 MHZ units, which is - the natural hardware unit for SKL */ - dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; - dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; - dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; - } /* hw_max = RP0 until we check for overclocking */ dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { ret = sandybridge_pcode_read(dev_priv, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, &ddcc_status); @@ -4318,6 +4311,16 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) dev_priv->rps.max_freq); } + if (IS_SKYLAKE(dev)) { + /* Store the frequency values in 16.66 MHZ units, which is + the natural hardware unit for SKL */ + dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; + dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; + dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; + dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; + dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; + } + dev_priv->rps.idle_freq = dev_priv->rps.min_freq; /* Preserve min/max settings in case of re-init */