Message ID | 1436837955-26279-5-git-send-email-rjui@broadcom.com (mailing list archive) |
---|---|
State | New, archived |
Delegated to: | Bjorn Helgaas |
Headers | show |
Hi, > +/dts-v1/; > + > +#include "ns2.dtsi" > + > +/ { > + model = "Broadcom NS2 SVK"; > + compatible = "brcm,ns2-svk", "brcm,ns2"; > + > + chosen { > + bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x66130000"; > + }; Please use stdout-path instead (you can use /aliases to make it simpler). It'll save a redundant description of the UART and will remove the dependency on Linux-specific naming of the UART. [...] > +/ { > + compatible = "brcm,ns2"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a57", "arm,armv8"; > + reg = <0 0>; > + enable-method = "spin-table"; > + cpu-release-addr = <0 0x84b00000>; > + }; > + }; Shouldn't the other CPUs be described? Using spin-table for SMP is somewhat unfortunate, as it comes with a number of problems (e.g. unwoken secondaries spinning in the kernel). I would strongly advise using PSCI instead. > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | > + IRQ_TYPE_EDGE_RISING)>, > + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | > + IRQ_TYPE_EDGE_RISING)>, > + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | > + IRQ_TYPE_EDGE_RISING)>, > + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | > + IRQ_TYPE_EDGE_RISING)>; > + clock-frequency = <25000000>; > + }; Please fix your firmware to configure CNTFRQ_EL0, it is simply a bug not to, and using clock-frequency does not fix all the problems that not configuring it causes. Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Monday 13 July 2015 18:39:15 Ray Jui wrote: > + chosen { > + bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x66130000"; > + }; > + Please remove those bootargs and just set the stdout-path to the alias of the uart. If necessary, you can have just "earlycon" in the bootargs. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 7/14/2015 2:23 AM, Mark Rutland wrote: > Hi, > >> +/dts-v1/; >> + >> +#include "ns2.dtsi" >> + >> +/ { >> + model = "Broadcom NS2 SVK"; >> + compatible = "brcm,ns2-svk", "brcm,ns2"; >> + >> + chosen { >> + bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x66130000"; >> + }; > > Please use stdout-path instead (you can use /aliases to make it > simpler). It'll save a redundant description of the UART and will remove > the dependency on Linux-specific naming of the UART. > > [...] Saw that Arnd also has the same comment. I will fix this. > >> +/ { >> + compatible = "brcm,ns2"; >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a57", "arm,armv8"; >> + reg = <0 0>; >> + enable-method = "spin-table"; >> + cpu-release-addr = <0 0x84b00000>; >> + }; >> + }; > > Shouldn't the other CPUs be described? Let me give that a try but there's a chance that I cannot enable other 3 cores until we have a more stable bootloader configuration. > > Using spin-table for SMP is somewhat unfortunate, as it comes with a > number of problems (e.g. unwoken secondaries spinning in the kernel). I > would strongly advise using PSCI instead. > Yes I agree and I'm fully aware PSCI is the preferred way of bringing up ARMv8 cores. Unfortunately this is currently out of my control as this is done in ARM Trusted Firmware that was handled by a different team within Broadcom and they have very tight schedule and will not have time to add PSCI support in the near term. The plan is to use spin-table for now and convert to PSCI when we have the support for it in our ATF. That should happen within the next couple months. >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | >> + IRQ_TYPE_EDGE_RISING)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | >> + IRQ_TYPE_EDGE_RISING)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | >> + IRQ_TYPE_EDGE_RISING)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | >> + IRQ_TYPE_EDGE_RISING)>; >> + clock-frequency = <25000000>; >> + }; > > Please fix your firmware to configure CNTFRQ_EL0, it is simply a bug not > to, and using clock-frequency does not fix all the problems that not > configuring it causes. Yes will do this. > > Thanks, > Mark. > Thanks, Ray -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/arm/bcm/ns2.txt b/Documentation/devicetree/bindings/arm/bcm/ns2.txt new file mode 100644 index 0000000..35f056f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/ns2.txt @@ -0,0 +1,9 @@ +Broadcom North Star 2 (NS2) device tree bindings +------------------------------------------------ + +Boards with NS2 shall have the following properties: + +Required root node property: + +NS2 SVK board +compatible = "brcm,ns2-svk", "brcm,ns2"; diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 38913be..9f95941 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,6 +1,7 @@ dts-dirs += amd dts-dirs += apm dts-dirs += arm +dts-dirs += broadcom dts-dirs += cavium dts-dirs += exynos dts-dirs += freescale diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile new file mode 100644 index 0000000..9fda762 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -0,0 +1,5 @@ +dtb-$(CONFIG_ARCH_BCM_NS2) += ns2-svk.dtb + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts new file mode 100644 index 0000000..08a7816 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -0,0 +1,55 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "ns2.dtsi" + +/ { + model = "Broadcom NS2 SVK"; + compatible = "brcm,ns2-svk", "brcm,ns2"; + + chosen { + bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x66130000"; + }; + + memory { + device_type = "memory"; + reg = <0x000000000 0x80000000 0x00000000 0x40000000>; + }; + + soc: soc { + uart3: serial@66130000 { + status = "ok"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi new file mode 100644 index 0000000..9d34fe4 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -0,0 +1,95 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/memreserve/ 0x84b00000 0x00000008; + +/ { + compatible = "brcm,ns2"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0 0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x84b00000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | + IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | + IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | + IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | + IRQ_TYPE_EDGE_RISING)>; + clock-frequency = <25000000>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + gic: interrupt-controller@65210000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x65210000 0x1000>, + <0x65220000 0x1000>, + <0x65240000 0x2000>, + <0x65260000 0x1000>; + }; + + uart3: serial@66130000 { + compatible = "snps,dw-apb-uart"; + reg = <0x66130000 0x100>; + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <23961600>; + status = "disabled"; + }; + }; +};