| Message ID | 1437063498-31930-1-git-send-email-michel.thierry@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jul 16, 2015 at 05:18:18PM +0100, Michel Thierry wrote: > Commit c44ef60e4370 ("drm/i915/gtt: Allow >= 4GB sizes for vm.") took care > of most of this changes, but i915_gem_obj_offset still returned an unsigned > long, which in only 4-bytes long in 32-bit kernels. > > Change return type (and other related offset variables) to u64. > > Since Global GTT is always limited to 4GB, this change is not required > in i915_gem_obj_ggtt_offset. > > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > Signed-off-by: Michel Thierry <michel.thierry@intel.com> > --- > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index fd17204..0cc6bf9 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4390,15 +4390,16 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj, > return -EBUSY; > > if (i915_vma_misplaced(vma, alignment, flags)) { > - unsigned long offset; > + u64 offset; > offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) : > i915_gem_obj_offset(obj, vm); We don't need offset here since we already have vma->node.start -Chris
On 07/16/2015 05:18 PM, Michel Thierry wrote: > Commit c44ef60e4370 ("drm/i915/gtt: Allow >= 4GB sizes for vm.") took care > of most of this changes, but i915_gem_obj_offset still returned an unsigned > long, which in only 4-bytes long in 32-bit kernels. > > Change return type (and other related offset variables) to u64. > > Since Global GTT is always limited to 4GB, this change is not required > in i915_gem_obj_ggtt_offset. Although in another patch dealing with GGTT I was asked to use u64 explicitly so how to make sure we get some consistency in this area? Regards, Tvrtko
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index aa9ce8f..1afaf1d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2974,9 +2974,8 @@ void i915_gem_restore_fences(struct drm_device *dev); unsigned long i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, const struct i915_ggtt_view *view); -unsigned long -i915_gem_obj_offset(struct drm_i915_gem_object *o, - struct i915_address_space *vm); +u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, + struct i915_address_space *vm); static inline unsigned long i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fd17204..0cc6bf9 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4390,15 +4390,16 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj, return -EBUSY; if (i915_vma_misplaced(vma, alignment, flags)) { - unsigned long offset; + u64 offset; offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) : i915_gem_obj_offset(obj, vm); WARN(vma->pin_count, "bo is already pinned in %s with incorrect alignment:" - " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," + " offset=%x %08x, req.alignment=%x, req.map_and_fenceable=%d," " obj->map_and_fenceable=%d\n", ggtt_view ? "ggtt" : "ppgtt", - offset, + upper_32_bits(offset), + lower_32_bits(offset), alignment, !!(flags & PIN_MAPPABLE), obj->map_and_fenceable); @@ -5379,9 +5380,8 @@ void i915_gem_track_fb(struct drm_i915_gem_object *old, } /* All the new VM stuff */ -unsigned long -i915_gem_obj_offset(struct drm_i915_gem_object *o, - struct i915_address_space *vm) +u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, + struct i915_address_space *vm) { struct drm_i915_private *dev_priv = o->base.dev->dev_private; struct i915_vma *vma; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 53629c7..b9db4df 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2505,9 +2505,9 @@ static void i915_gtt_color_adjust(struct drm_mm_node *node, } static int i915_gem_setup_global_gtt(struct drm_device *dev, - unsigned long start, - unsigned long mappable_end, - unsigned long end) + u64 start, + u64 mappable_end, + u64 end) { /* Let GEM Manage all of the aperture. * diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 70c50e7..8275007 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -149,7 +149,7 @@ struct i915_ggtt_view { union { struct { - unsigned long offset; + u64 offset; unsigned int size; } partial; } params;
Commit c44ef60e4370 ("drm/i915/gtt: Allow >= 4GB sizes for vm.") took care of most of this changes, but i915_gem_obj_offset still returned an unsigned long, which in only 4-bytes long in 32-bit kernels. Change return type (and other related offset variables) to u64. Since Global GTT is always limited to 4GB, this change is not required in i915_gem_obj_ggtt_offset. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Michel Thierry <michel.thierry@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 5 ++--- drivers/gpu/drm/i915/i915_gem.c | 12 ++++++------ drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++--- drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +- 4 files changed, 12 insertions(+), 13 deletions(-)