| Message ID | 1436466554-24806-7-git-send-email-david.s.gordon@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jul 09, 2015 at 07:29:07PM +0100, Dave Gordon wrote: > GuC submission is basically execlist submission, but with the GuC > handling the actual writes to the ELSP and the resulting context > switch interrupts. So to prepare a context for submission via the > GuC, we need some of the same functions used in execlist mode. > This commit exposes two such functions, changing their names to > better describe what they do (they're related to logical ring > contexts rather than to execlists per se). > > v2: > Replaces previous "drm/i915: Move execlists defines from .c to .h" > > v3: > Incorporates a change to one of the functions exposed here that was > previously part of an internal patch, but which was omitted from > the version recently committed to drm-intel-nightly: > 7a01a0a drm/i915/lrc: Update PDPx registers with lri commands > So we reinstate this change here. > > v4: > Drop v3 change, update function parameters due to collision with > 8ee3615 drm/i915: Convert execlists_ctx_descriptor() for requests > > Issue: VIZ-4884 > Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 21 ++++++++++----------- > drivers/gpu/drm/i915/intel_lrc.h | 3 +++ > 2 files changed, 13 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index d4f8b43..9e121d3 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -261,11 +261,11 @@ u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) > return lrca >> 12; > } > > -static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_request *rq) > +uint64_t intel_lr_context_descriptor(struct intel_context *ctx, > + struct intel_engine_cs *ring) > { > - struct intel_engine_cs *ring = rq->ring; > struct drm_device *dev = ring->dev; > - struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; > + struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; > uint64_t desc; > uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); > > @@ -303,13 +303,13 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0, > uint64_t desc[2]; > > if (rq1) { > - desc[1] = execlists_ctx_descriptor(rq1); > + desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring); > rq1->elsp_submitted++; > } else { > desc[1] = 0; > } > > - desc[0] = execlists_ctx_descriptor(rq0); > + desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring); > rq0->elsp_submitted++; > > /* You must always write both descriptors in the order below. */ > @@ -328,7 +328,8 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0, > spin_unlock(&dev_priv->uncore.lock); > } > > -static int execlists_update_context(struct drm_i915_gem_request *rq) > +/* Update the ringbuffer pointer and tail offset in a saved context image */ > +void intel_lr_context_update(struct drm_i915_gem_request *rq) > { > struct intel_engine_cs *ring = rq->ring; > struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; > @@ -358,17 +359,15 @@ static int execlists_update_context(struct drm_i915_gem_request *rq) > } > > kunmap_atomic(reg_state); > - > - return 0; > } > > static void execlists_submit_requests(struct drm_i915_gem_request *rq0, > struct drm_i915_gem_request *rq1) > { > - execlists_update_context(rq0); > + intel_lr_context_update(rq0); > > if (rq1) > - execlists_update_context(rq1); > + intel_lr_context_update(rq1); > > execlists_elsp_write(rq0, rq1); > } > @@ -2051,7 +2050,7 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o > reg_state[CTX_RING_TAIL+1] = 0; > reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); > /* Ring buffer start address is not known until the buffer is pinned. > - * It is written to the context image in execlists_update_context() > + * It is written to the context image in intel_lr_context_update() > */ > reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); > reg_state[CTX_RING_BUFFER_CONTROL+1] = > diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h > index e0299fb..6ecc0b3 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.h > +++ b/drivers/gpu/drm/i915/intel_lrc.h > @@ -73,6 +73,9 @@ int intel_lr_context_deferred_create(struct intel_context *ctx, > void intel_lr_context_unpin(struct drm_i915_gem_request *req); > void intel_lr_context_reset(struct drm_device *dev, > struct intel_context *ctx); > +void intel_lr_context_update(struct drm_i915_gem_request *rq); > +uint64_t intel_lr_context_descriptor(struct intel_context *ctx, > + struct intel_engine_cs *ring); > > /* Execlists */ > int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists); > -- > 1.9.1 >
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index d4f8b43..9e121d3 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -261,11 +261,11 @@ u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) return lrca >> 12; } -static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_request *rq) +uint64_t intel_lr_context_descriptor(struct intel_context *ctx, + struct intel_engine_cs *ring) { - struct intel_engine_cs *ring = rq->ring; struct drm_device *dev = ring->dev; - struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; + struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; uint64_t desc; uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); @@ -303,13 +303,13 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0, uint64_t desc[2]; if (rq1) { - desc[1] = execlists_ctx_descriptor(rq1); + desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring); rq1->elsp_submitted++; } else { desc[1] = 0; } - desc[0] = execlists_ctx_descriptor(rq0); + desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring); rq0->elsp_submitted++; /* You must always write both descriptors in the order below. */ @@ -328,7 +328,8 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0, spin_unlock(&dev_priv->uncore.lock); } -static int execlists_update_context(struct drm_i915_gem_request *rq) +/* Update the ringbuffer pointer and tail offset in a saved context image */ +void intel_lr_context_update(struct drm_i915_gem_request *rq) { struct intel_engine_cs *ring = rq->ring; struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; @@ -358,17 +359,15 @@ static int execlists_update_context(struct drm_i915_gem_request *rq) } kunmap_atomic(reg_state); - - return 0; } static void execlists_submit_requests(struct drm_i915_gem_request *rq0, struct drm_i915_gem_request *rq1) { - execlists_update_context(rq0); + intel_lr_context_update(rq0); if (rq1) - execlists_update_context(rq1); + intel_lr_context_update(rq1); execlists_elsp_write(rq0, rq1); } @@ -2051,7 +2050,7 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o reg_state[CTX_RING_TAIL+1] = 0; reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); /* Ring buffer start address is not known until the buffer is pinned. - * It is written to the context image in execlists_update_context() + * It is written to the context image in intel_lr_context_update() */ reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); reg_state[CTX_RING_BUFFER_CONTROL+1] = diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index e0299fb..6ecc0b3 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -73,6 +73,9 @@ int intel_lr_context_deferred_create(struct intel_context *ctx, void intel_lr_context_unpin(struct drm_i915_gem_request *req); void intel_lr_context_reset(struct drm_device *dev, struct intel_context *ctx); +void intel_lr_context_update(struct drm_i915_gem_request *rq); +uint64_t intel_lr_context_descriptor(struct intel_context *ctx, + struct intel_engine_cs *ring); /* Execlists */ int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
GuC submission is basically execlist submission, but with the GuC handling the actual writes to the ELSP and the resulting context switch interrupts. So to prepare a context for submission via the GuC, we need some of the same functions used in execlist mode. This commit exposes two such functions, changing their names to better describe what they do (they're related to logical ring contexts rather than to execlists per se). v2: Replaces previous "drm/i915: Move execlists defines from .c to .h" v3: Incorporates a change to one of the functions exposed here that was previously part of an internal patch, but which was omitted from the version recently committed to drm-intel-nightly: 7a01a0a drm/i915/lrc: Update PDPx registers with lri commands So we reinstate this change here. v4: Drop v3 change, update function parameters due to collision with 8ee3615 drm/i915: Convert execlists_ctx_descriptor() for requests Issue: VIZ-4884 Signed-off-by: Dave Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 21 ++++++++++----------- drivers/gpu/drm/i915/intel_lrc.h | 3 +++ 2 files changed, 13 insertions(+), 11 deletions(-)