| Message ID | 1437062889-29196-1-git-send-email-damien.lespiau@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
> -----Original Message----- > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of > Damien Lespiau > Sent: Thursday, July 16, 2015 9:08 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 1/2] drm/i915/skl: Don't expose the top most plane > on gen9 display > > on SKL/BXT, the top most plane hardware is shared between the legacy > cursor registers and an actual plane. Daniel and Ville don't want to > expose 2 DRM planes and would rather expose a CURSOR plane that has all > the usual plane properties, and that's a blocker for lifting the > prelimary_hw_support flag. > > Unfortunately noone has had the time to finish this yet, but lifting the > prelimary_hw_support flag is long overdue. As an intermediate solution > we can merely not expose the top most plane > > Cc: Imre Deak <imre.deak@intel.com> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > --- > drivers/gpu/drm/i915/i915_dma.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_dma.c > b/drivers/gpu/drm/i915/i915_dma.c > index 91925cb..96564cd 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -726,11 +726,19 @@ static void intel_device_info_runtime_init(struct > drm_device *dev) > > info = (struct intel_device_info *)&dev_priv->info; > > + /* > + * Skylake and Broxton currently don't expose the topmost plane as its > + * use is exclusive with the legacy cursor and we only want to expose > + * one of those, not both. Until we can safely expose the topmost plane > + * as a DRM_PLANE_TYPE_CURSOR with all the features > exposed/supported, > + * we don't expose the topmost plane at all to prevent ABI breakage > + * down the line. > + */ > if (IS_BROXTON(dev)) { > - info->num_sprites[PIPE_A] = 3; > - info->num_sprites[PIPE_B] = 3; > - info->num_sprites[PIPE_C] = 2; > - } else if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9) > + info->num_sprites[PIPE_A] = 2; > + info->num_sprites[PIPE_B] = 2; > + info->num_sprites[PIPE_C] = 1; > + } else if (IS_VALLEYVIEW(dev)) > for_each_pipe(dev_priv, pipe) > info->num_sprites[pipe] = 2; For SKL, by default you can keep as 2 planes + 1 cursor, but let userland change to 3 planes + no cursor. This is a one-time request only and not ping ponging between 2+1 and 3+0. For Android, this gives flexibility to use 3 planes where cursor isn't a dominant case. Similarly, for BXT, allow 4+0 and keep 3+1 as default for legacy userlands. > else > -- > 2.1.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> -----Original Message----- > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of > Damien Lespiau > Sent: Thursday, July 16, 2015 9:08 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 1/2] drm/i915/skl: Don't expose the top most plane > on gen9 display > > on SKL/BXT, the top most plane hardware is shared between the legacy > cursor registers and an actual plane. Daniel and Ville don't want to > expose 2 DRM planes and would rather expose a CURSOR plane that has all > the usual plane properties, and that's a blocker for lifting the > prelimary_hw_support flag. > > Unfortunately noone has had the time to finish this yet, but lifting the > prelimary_hw_support flag is long overdue. As an intermediate solution > we can merely not expose the top most plane > > Cc: Imre Deak <imre.deak@intel.com> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > --- > drivers/gpu/drm/i915/i915_dma.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_dma.c > b/drivers/gpu/drm/i915/i915_dma.c > index 91925cb..96564cd 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -726,11 +726,19 @@ static void intel_device_info_runtime_init(struct > drm_device *dev) > > info = (struct intel_device_info *)&dev_priv->info; > > + /* > + * Skylake and Broxton currently don't expose the topmost plane as its > + * use is exclusive with the legacy cursor and we only want to expose > + * one of those, not both. Until we can safely expose the topmost plane > + * as a DRM_PLANE_TYPE_CURSOR with all the features > exposed/supported, > + * we don't expose the topmost plane at all to prevent ABI breakage > + * down the line. > + */ > if (IS_BROXTON(dev)) { > - info->num_sprites[PIPE_A] = 3; > - info->num_sprites[PIPE_B] = 3; > - info->num_sprites[PIPE_C] = 2; > - } else if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9) > + info->num_sprites[PIPE_A] = 2; > + info->num_sprites[PIPE_B] = 2; > + info->num_sprites[PIPE_C] = 1; > + } else if (IS_VALLEYVIEW(dev)) > for_each_pipe(dev_priv, pipe) > info->num_sprites[pipe] = 2; By the way, this is breaking kms_plane_scaling where 3rd plane used as regular plane as it was allowed before by kernel. There may be other igts also impacted by this change. > else > -- > 2.1.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 91925cb..96564cd 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -726,11 +726,19 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info = (struct intel_device_info *)&dev_priv->info; + /* + * Skylake and Broxton currently don't expose the topmost plane as its + * use is exclusive with the legacy cursor and we only want to expose + * one of those, not both. Until we can safely expose the topmost plane + * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, + * we don't expose the topmost plane at all to prevent ABI breakage + * down the line. + */ if (IS_BROXTON(dev)) { - info->num_sprites[PIPE_A] = 3; - info->num_sprites[PIPE_B] = 3; - info->num_sprites[PIPE_C] = 2; - } else if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9) + info->num_sprites[PIPE_A] = 2; + info->num_sprites[PIPE_B] = 2; + info->num_sprites[PIPE_C] = 1; + } else if (IS_VALLEYVIEW(dev)) for_each_pipe(dev_priv, pipe) info->num_sprites[pipe] = 2; else
on SKL/BXT, the top most plane hardware is shared between the legacy cursor registers and an actual plane. Daniel and Ville don't want to expose 2 DRM planes and would rather expose a CURSOR plane that has all the usual plane properties, and that's a blocker for lifting the prelimary_hw_support flag. Unfortunately noone has had the time to finish this yet, but lifting the prelimary_hw_support flag is long overdue. As an intermediate solution we can merely not expose the top most plane Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> --- drivers/gpu/drm/i915/i915_dma.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-)