| Message ID | 873801w377.wl%kuninori.morimoto.gx@renesas.com (mailing list archive) |
|---|---|
| State | RFC |
| Delegated to: | Simon Horman |
| Headers | show |
Hi > diff --git a/include/dt-bindings/clock/r8a7795-clock.h b/include/dt-bindings/clock/r8a7795-clock.h > new file mode 100644 > index 0000000..fc1c4da > --- /dev/null > +++ b/include/dt-bindings/clock/r8a7795-clock.h > @@ -0,0 +1,31 @@ > +#ifndef __DT_BINDINGS_CLOCK_RCAR_GEN3_H__ > +#define __DT_BINDINGS_CLOCK_RCAR_GEN3_H__ > + > +/* CPG */ > +#define RCAR_GEN3_CLK_MAIN 0 > +#define RCAR_GEN3_CLK_PLL0 1 > +#define RCAR_GEN3_CLK_PLL1 2 > +#define RCAR_GEN3_CLK_PLL2 3 > +#define RCAR_GEN3_CLK_PLL3 4 > +#define RCAR_GEN3_CLK_PLL4 5 (snip) About this, file name is r8a7795-clock.h, and it is using GEN3 for each definition. I thought all Gen3 series (will) have compatible mapping, but maybe it can't. So, maybe using SoC naming (same as before) in v4 is good idea. -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Morimoto-san, Thank you for the patch. On Monday 03 August 2015 01:53:23 Kuninori Morimoto wrote: > From: Gaku Inami <gaku.inami.xw@bp.renesas.com> > > Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> > Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > --- > v2 -> v3 > > - no change > > Documentation/devicetree/bindings/arm/shmobile.txt | 2 + > .../bindings/clock/renesas,cpg-mstp-clocks.txt | 1 + > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/renesas/Makefile | 5 ++ > arch/arm64/boot/dts/renesas/r8a7795.dtsi | 93 +++++++++++++++++++ > include/dt-bindings/clock/r8a7795-clock.h | 31 ++++++++ > 6 files changed, 133 insertions(+) > create mode 100644 arch/arm64/boot/dts/renesas/Makefile > create mode 100644 arch/arm64/boot/dts/renesas/r8a7795.dtsi > create mode 100644 include/dt-bindings/clock/r8a7795-clock.h [snip] > diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > b/arch/arm64/boot/dts/renesas/r8a7795.dtsi new file mode 100644 > index 0000000..0f298c3 > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > @@ -0,0 +1,93 @@ > +/* > + * Device Tree Source for the r8a7795 SoC > + * > + * Copyright (C) 2015 Renesas Electronics Corp. > + * > + * This file is licensed under the terms of the GNU General Public License > + * version 2. This program is licensed "as is" without any warranty of any > + * kind, whether express or implied. > + */ > + > +#include <dt-bindings/clock/r8a7795-clock.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + compatible = "renesas,r8a7795"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* 1core only at this point */ > + a57_0: cpu@0 { > + compatible = "arm,cortex-a57", "arm,armv8"; > + reg = <0x0>; > + device_type = "cpu"; > + }; > + }; > + > + gic: interrupt-controller@0xf1010000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x0 0xf1010000 0 0x1000>, > + <0x0 0xf1020000 0 0x2000>; > + interrupts = <GIC_PPI 9 > + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; > + }; Shouldn't the memory-mapped peripherals be put under a bus node instead of the root DT node ? > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 > + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 > + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 > + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 > + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; > + }; > + > + clocks { Let's try to make it right from the start on Gen3. The CPG node should be a direct child of the bus node mentioned above, and the MSTP clocks should be children of the CPG node. I'm not sure where to put the non-memory-mapped clocks though, should they be directly under the root node ? It would make sense for extal_clk, but how about the fixed-factor clocks ? Should they be children of the CPG node too ? > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + extal_clk: extal_clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <0>; > + clock-output-names = "extal"; > + }; > + cpg_clocks: cpg_clocks@e6150000 { > + compatible = "renesas,r8a7795-cpg-clocks", > + "renesas,rcar-gen3-cpg-clocks"; > + reg = <0 0xe6150000 0 0x1000>; > + clocks = <&extal_clk>; > + #clock-cells = <1>; > + clock-output-names = "main", "pll0", "pll1","pll2", > + "pll3", "pll4"; > + }; > + p_clk: p_clk { > + compatible = "fixed-factor-clock"; > + clocks = <&cpg_clocks RCAR_GEN3_CLK_PLL1>; > + #clock-cells = <0>; > + clock-div = <24>; > + clock-mult = <1>; > + clock-output-names = "p"; > + }; > + mstp3_clks: mstp3_clks@e615013c { > + compatible = "renesas,r8a7795-mstp-clocks", > + "renesas,cpg-mstp-clocks"; > + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; > + clocks = <&p_clk>; > + #clock-cells = <1>; > + renesas,clock-indices = <RCAR_GEN3_CLK_IRDA>; > + clock-output-names = "irda"; > + }; > + }; > +};
On Tue, Aug 4, 2015 at 2:22 PM, Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: > On Monday 03 August 2015 01:53:23 Kuninori Morimoto wrote: >> --- /dev/null >> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi >> @@ -0,0 +1,93 @@ >> +/ { >> + clocks { > > Let's try to make it right from the start on Gen3. The CPG node should be a > direct child of the bus node mentioned above, and the MSTP clocks should be > children of the CPG node. Agreed. > I'm not sure where to put the non-memory-mapped clocks though, should they be > directly under the root node ? It would make sense for extal_clk, but how > about the fixed-factor clocks ? Should they be children of the CPG node too ? I believe the current trend is to put clocks like "extal_clk" under the root node. As the fixed-factor clocks are generated by the CPG module, and we do have a device node for it, I'd make them children of the CPG node, too. Any comments from the clk+dt experts? Thanks! >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + extal_clk: extal_clk { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <0>; >> + clock-output-names = "extal"; >> + }; >> + cpg_clocks: cpg_clocks@e6150000 { >> + compatible = "renesas,r8a7795-cpg-clocks", >> + "renesas,rcar-gen3-cpg-clocks"; >> + reg = <0 0xe6150000 0 0x1000>; >> + clocks = <&extal_clk>; >> + #clock-cells = <1>; >> + clock-output-names = "main", "pll0", "pll1","pll2", >> + "pll3", "pll4"; >> + }; >> + p_clk: p_clk { >> + compatible = "fixed-factor-clock"; >> + clocks = <&cpg_clocks RCAR_GEN3_CLK_PLL1>; >> + #clock-cells = <0>; >> + clock-div = <24>; >> + clock-mult = <1>; >> + clock-output-names = "p"; >> + }; >> + mstp3_clks: mstp3_clks@e615013c { >> + compatible = "renesas,r8a7795-mstp-clocks", >> + "renesas,cpg-mstp-clocks"; >> + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; >> + clocks = <&p_clk>; >> + #clock-cells = <1>; >> + renesas,clock-indices = <RCAR_GEN3_CLK_IRDA>; >> + clock-output-names = "irda"; >> + }; >> + }; >> +}; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Quoting Geert Uytterhoeven (2015-08-04 05:34:06) > On Tue, Aug 4, 2015 at 2:22 PM, Laurent Pinchart > <laurent.pinchart@ideasonboard.com> wrote: > > On Monday 03 August 2015 01:53:23 Kuninori Morimoto wrote: > >> --- /dev/null > >> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > >> @@ -0,0 +1,93 @@ > >> +/ { > > >> + clocks { > > > > Let's try to make it right from the start on Gen3. The CPG node should be a > > direct child of the bus node mentioned above, and the MSTP clocks should be > > children of the CPG node. > > Agreed. > > > I'm not sure where to put the non-memory-mapped clocks though, should they be > > directly under the root node ? It would make sense for extal_clk, but how > > about the fixed-factor clocks ? Should they be children of the CPG node too ? > > I believe the current trend is to put clocks like "extal_clk" under the root > node. > As the fixed-factor clocks are generated by the CPG module, and we do have > a device node for it, I'd make them children of the CPG node, too. > > Any comments from the clk+dt experts? I don't know if anyone is an expert ;-) extal_clk should be under the root node. That is true for all board-level clocks and clock controllers. Within the SoC we want to model the clock controller as a node in DT, not necessarily all of the individual clocks. So you definitely need a "cpg" node in DT with #clock-cells > 0. Whether or not you enumerate the individual clocks in DT is up to you. I do not like the data-driven approach of putting the clock definition data into DT. It makes it awkward to do things like set a flag on a single clock later on. Simply using the clock controller phandle plus one or more offsets is preferred over a per-clock phandle. Stephen and I have been discussing what a formal clock-controller binding would look like, and one item we came up with is that any sub-nodes of the controller would not be allowed to have a #clock-cells property. Also, while you're thinking about the perfect clock binding, please do consider dropping clock-output-names if you can. Specifying clock-names alongside the clocks property inside of the consumer node is a bit more elegant in my opinion. This is also a bit easier if you think about expressing your clock data with C inside of your provider driver. Regards, Mike > > Thanks! > > >> + #address-cells = <2>; > >> + #size-cells = <2>; > >> + ranges; > >> + > >> + extal_clk: extal_clk { > >> + compatible = "fixed-clock"; > >> + #clock-cells = <0>; > >> + clock-frequency = <0>; > >> + clock-output-names = "extal"; > >> + }; > >> + cpg_clocks: cpg_clocks@e6150000 { > >> + compatible = "renesas,r8a7795-cpg-clocks", > >> + "renesas,rcar-gen3-cpg-clocks"; > >> + reg = <0 0xe6150000 0 0x1000>; > >> + clocks = <&extal_clk>; > >> + #clock-cells = <1>; > >> + clock-output-names = "main", "pll0", "pll1","pll2", > >> + "pll3", "pll4"; > >> + }; > >> + p_clk: p_clk { > >> + compatible = "fixed-factor-clock"; > >> + clocks = <&cpg_clocks RCAR_GEN3_CLK_PLL1>; > >> + #clock-cells = <0>; > >> + clock-div = <24>; > >> + clock-mult = <1>; > >> + clock-output-names = "p"; > >> + }; > >> + mstp3_clks: mstp3_clks@e615013c { > >> + compatible = "renesas,r8a7795-mstp-clocks", > >> + "renesas,cpg-mstp-clocks"; > >> + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; > >> + clocks = <&p_clk>; > >> + #clock-cells = <1>; > >> + renesas,clock-indices = <RCAR_GEN3_CLK_IRDA>; > >> + clock-output-names = "irda"; > >> + }; > >> + }; > >> +}; > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds > -- > To unsubscribe from this list: send the line "unsubscribe linux-clk" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index c4f19b2..8d696a0 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -27,6 +27,8 @@ SoCs: compatible = "renesas,r8a7793" - R-Car E2 (R8A77940) compatible = "renesas,r8a7794" + - R-Car H3 (R8A77950) + compatible = "renesas,r8a7795" Boards: diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index 16ed181..4169c76 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt @@ -19,6 +19,7 @@ Required Properties: - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks + - "renesas,r8a7795-mstp-clocks" for R8A7795 (R-Car H3) MSTP gate clocks - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks and "renesas,cpg-mstp-clocks" as a fallback. - reg: Base address and length of the I/O mapped registers used by the MSTP diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 38913be2..5691ca4 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -7,6 +7,7 @@ dts-dirs += freescale dts-dirs += hisilicon dts-dirs += mediatek dts-dirs += qcom +dts-dirs += renesas dts-dirs += sprd dts-dirs += xilinx diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile new file mode 100644 index 0000000..6aeefd9 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -0,0 +1,5 @@ +dtb-$(CONFIG_ARCH_RCAR_GEN3) += + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi new file mode 100644 index 0000000..0f298c3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -0,0 +1,93 @@ +/* + * Device Tree Source for the r8a7795 SoC + * + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/clock/r8a7795-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "renesas,r8a7795"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* 1core only at this point */ + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + }; + }; + + gic: interrupt-controller@0xf1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "extal"; + }; + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7795-cpg-clocks", + "renesas,rcar-gen3-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1","pll2", + "pll3", "pll4"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks RCAR_GEN3_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7795-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = <RCAR_GEN3_CLK_IRDA>; + clock-output-names = "irda"; + }; + }; +}; diff --git a/include/dt-bindings/clock/r8a7795-clock.h b/include/dt-bindings/clock/r8a7795-clock.h new file mode 100644 index 0000000..fc1c4da --- /dev/null +++ b/include/dt-bindings/clock/r8a7795-clock.h @@ -0,0 +1,31 @@ +#ifndef __DT_BINDINGS_CLOCK_RCAR_GEN3_H__ +#define __DT_BINDINGS_CLOCK_RCAR_GEN3_H__ + +/* CPG */ +#define RCAR_GEN3_CLK_MAIN 0 +#define RCAR_GEN3_CLK_PLL0 1 +#define RCAR_GEN3_CLK_PLL1 2 +#define RCAR_GEN3_CLK_PLL2 3 +#define RCAR_GEN3_CLK_PLL3 4 +#define RCAR_GEN3_CLK_PLL4 5 + +/* MSTP0 */ + +/* MSTP1 */ + +/* MSTP2 */ + +/* MSTP3 */ +#define RCAR_GEN3_CLK_IRDA 10 + +/* MSTP5 */ + +/* MSTP7 */ + +/* MSTP8 */ + +/* MSTP9 */ + +/* MSTP10 */ + +#endif /* __DT_BINDINGS_CLOCK_RCAR_GEN3_H__ */