| Message ID | 87bne2b9fv.wl%kuninori.morimoto.gx@renesas.com (mailing list archive) |
|---|---|
| State | RFC |
| Headers | show |
On Thu, Aug 20, 2015 at 09:26:47AM +0000, Kuninori Morimoto wrote: > From: Gaku Inami <gaku.inami.xw@bp.renesas.com> > > This patch enables SCIF2 > Gaku Inami <gaku.inami.xw@bp.renesas.com> created original patch, > and Kuninori updated DTSI > > Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> > Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > --- > v5 -> v6 > > - cpg has #clock-cells > > arch/arm64/boot/dts/renesas/r8a7795.dtsi | 21 +++++++++++++++++++++ > include/dt-bindings/clock/r8a7795-clock.h | 1 + > 2 files changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > index f013814..7bf9f56 100644 > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > @@ -49,10 +49,23 @@ > }; > > cpg_clocks: cpg_clocks@e6150000 { > + #address-cells = <2>; > + #size-cells = <2>; > + #clock-cells = <1>; > + ranges; > + > compatible = "renesas,r8a7795-cpg-clocks", > "renesas,rcar-gen3-cpg-clocks"; > reg = <0 0xe6150000 0 0x1000>; > clocks = <&extal_clk>; > + > + mstp3_clks: mstp3_clks@e615013c { > + compatible = "renesas,r8a7795-mstp-clocks", > + "renesas,cpg-mstp-clocks"; > + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; > + clocks = <&s3d4_clks>; > + renesas,clock-indices = <R8A7795_CLK_SCIF2>; > + }; > }; > }; Is it intentional that the clock-output-names property is not present in the mstp3_clks node? It was present in the previous revision of this patch. [snip] -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Simon, On Thu, Aug 20, 2015 at 8:53 PM, Simon Horman <horms@verge.net.au> wrote: >> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi >> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi >> @@ -49,10 +49,23 @@ >> }; >> >> cpg_clocks: cpg_clocks@e6150000 { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + #clock-cells = <1>; >> + ranges; >> + >> compatible = "renesas,r8a7795-cpg-clocks", >> "renesas,rcar-gen3-cpg-clocks"; >> reg = <0 0xe6150000 0 0x1000>; >> clocks = <&extal_clk>; >> + >> + mstp3_clks: mstp3_clks@e615013c { >> + compatible = "renesas,r8a7795-mstp-clocks", >> + "renesas,cpg-mstp-clocks"; >> + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; >> + clocks = <&s3d4_clks>; >> + renesas,clock-indices = <R8A7795_CLK_SCIF2>; >> + }; >> }; >> }; > > Is it intentional that the clock-output-names property is not present in > the mstp3_clks node? It was present in the previous revision of this patch. Yes, cfr. Mike's response in "Re: [PATCH 3/4 v3][RFC] arm64: renesas: Add initial r8a7795 SoC support" (http://www.spinics.net/lists/devicetree/msg90740.html). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Aug 20, 2015 at 09:14:32PM +0200, Geert Uytterhoeven wrote: > Hi Simon, > > On Thu, Aug 20, 2015 at 8:53 PM, Simon Horman <horms@verge.net.au> wrote: > >> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > >> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > >> @@ -49,10 +49,23 @@ > >> }; > >> > >> cpg_clocks: cpg_clocks@e6150000 { > >> + #address-cells = <2>; > >> + #size-cells = <2>; > >> + #clock-cells = <1>; > >> + ranges; > >> + > >> compatible = "renesas,r8a7795-cpg-clocks", > >> "renesas,rcar-gen3-cpg-clocks"; > >> reg = <0 0xe6150000 0 0x1000>; > >> clocks = <&extal_clk>; > >> + > >> + mstp3_clks: mstp3_clks@e615013c { > >> + compatible = "renesas,r8a7795-mstp-clocks", > >> + "renesas,cpg-mstp-clocks"; > >> + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; > >> + clocks = <&s3d4_clks>; > >> + renesas,clock-indices = <R8A7795_CLK_SCIF2>; > >> + }; > >> }; > >> }; > > > > Is it intentional that the clock-output-names property is not present in > > the mstp3_clks node? It was present in the previous revision of this patch. > > Yes, cfr. Mike's response in "Re: [PATCH 3/4 v3][RFC] arm64: renesas: Add > initial r8a7795 SoC support" > (http://www.spinics.net/lists/devicetree/msg90740.html). Thanks, got it. -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index f013814..7bf9f56 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -49,10 +49,23 @@ }; cpg_clocks: cpg_clocks@e6150000 { + #address-cells = <2>; + #size-cells = <2>; + #clock-cells = <1>; + ranges; + compatible = "renesas,r8a7795-cpg-clocks", "renesas,rcar-gen3-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; clocks = <&extal_clk>; + + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7795-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&s3d4_clks>; + renesas,clock-indices = <R8A7795_CLK_SCIF2>; + }; }; }; @@ -85,5 +98,13 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7795_CLK_SCIF2>; + clock-names = "sci_ick"; + }; }; }; diff --git a/include/dt-bindings/clock/r8a7795-clock.h b/include/dt-bindings/clock/r8a7795-clock.h index 334fa13..27b3a29 100644 --- a/include/dt-bindings/clock/r8a7795-clock.h +++ b/include/dt-bindings/clock/r8a7795-clock.h @@ -24,6 +24,7 @@ /* MSTP2 */ /* MSTP3 */ +#define R8A7795_CLK_SCIF2 10 /* MSTP5 */