diff mbox

[V2] drm/i915/skl+: Add YUV pixel format in Capability list

Message ID 1437141041-1078-1-git-send-email-mahesh1.kumar@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Kumar, Mahesh July 17, 2015, 1:50 p.m. UTC
GEN >= 9 supports YUV format for all planes, but it's not exported in
Capability list of primary plane. Add YUV formats in skl_primary_formats
list.
Don't rely on fb->bits_per_pixel as intel_framebuffer_init is not
filling bits_per_pixel field of fb-struct for YUV pixel format.
This leads to divide by zero error during watermark calculation.

V2: Don't break NV12 case.

Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
Cc: Konduru, Chandra <chandra.konduru@intel.com>
---

 IGT changes made for testcase will be sent in separate patch.

 drivers/gpu/drm/i915/intel_display.c | 4 ++++
 drivers/gpu/drm/i915/intel_pm.c      | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

Comments

Shuang He July 20, 2015, 7:28 a.m. UTC | #1
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6823
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                                  302/302              302/302
SNB                                  315/315              315/315
IVB                                  342/342              342/342
BYT                 -1              285/285              284/285
HSW                                  378/378              378/378
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*BYT  igt@gem_partial_pwrite_pread@reads-display      PASS(1)      FAIL(1)
Note: You need to pay more attention to line start with '*'
Ville Syrjala Aug. 24, 2015, 1:05 p.m. UTC | #2
On Fri, Jul 17, 2015 at 07:20:41PM +0530, Kumar, Mahesh wrote:
> GEN >= 9 supports YUV format for all planes, but it's not exported in
> Capability list of primary plane. Add YUV formats in skl_primary_formats
> list.
> Don't rely on fb->bits_per_pixel as intel_framebuffer_init is not
> filling bits_per_pixel field of fb-struct for YUV pixel format.
> This leads to divide by zero error during watermark calculation.
> 
> V2: Don't break NV12 case.
> 
> Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
> Cc: Konduru, Chandra <chandra.konduru@intel.com>
> ---
> 
>  IGT changes made for testcase will be sent in separate patch.
> 
>  drivers/gpu/drm/i915/intel_display.c | 4 ++++
>  drivers/gpu/drm/i915/intel_pm.c      | 3 ++-
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index af0bcfe..d31704a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -72,6 +72,10 @@ static const uint32_t skl_primary_formats[] = {
>  	DRM_FORMAT_ABGR8888,
>  	DRM_FORMAT_XRGB2101010,
>  	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
>  };
>  
>  /* Cursor formats */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5eeddc9..5768f8c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3164,7 +3164,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
>  		if (fb) {
>  			p->plane[0].enabled = true;
>  			p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
> -				drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
> +				drm_format_plane_cpp(fb->pixel_format, 1) :
> +				drm_format_plane_cpp(fb->pixel_format, 0);

Someone should really fix the SKL WM code to treat the Y plane as the
normal case and CbCr as the special case. Currently we do just the
opposite which leads to this kind of checks all over the place.

>  			p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
>  				drm_format_plane_cpp(fb->pixel_format, 0) : 0;
>  			p->plane[0].tiling = fb->modifier[0];
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index af0bcfe..d31704a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -72,6 +72,10 @@  static const uint32_t skl_primary_formats[] = {
 	DRM_FORMAT_ABGR8888,
 	DRM_FORMAT_XRGB2101010,
 	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
 };
 
 /* Cursor formats */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5eeddc9..5768f8c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3164,7 +3164,8 @@  static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
 		if (fb) {
 			p->plane[0].enabled = true;
 			p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
-				drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
+				drm_format_plane_cpp(fb->pixel_format, 1) :
+				drm_format_plane_cpp(fb->pixel_format, 0);
 			p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
 				drm_format_plane_cpp(fb->pixel_format, 0) : 0;
 			p->plane[0].tiling = fb->modifier[0];