Message ID | 1440667450-3513-2-git-send-email-horms+renesas@verge.net.au (mailing list archive) |
---|---|
State | Changes Requested |
Delegated to: | Simon Horman |
Headers | show |
Thanks for the patch. On Thu, Aug 27, 2015 at 11:24 AM, Simon Horman <horms+renesas@verge.net.au> wrote: > From: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > [horms: broken out of a larger patch; moved to soc node] > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > --- > arch/arm64/boot/dts/renesas/r8a7795.dtsi | 104 +++++++++++++++++++++++++++++++ > 1 file changed, 104 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > index 9fba8be62025..a608eb92a172 100644 > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > @@ -52,6 +52,110 @@ > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; > }; > > + gpio0: gpio@e6050000 { > + compatible = "renesas,gpio-r8a7795", > + "renesas,gpio-rcar"; > + reg = <0 0xe6050000 0 0x50>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&pfc 0 0 32>; > + #interrupt-cells = <2>; > + interrupt-controller; > + clocks = <&mstp9_clks R8A7795_CLK_GPIO0>; > + }; > + [...] > + gpio5: gpio@e6055000 { > + compatible = "renesas,gpio-r8a7795", > + "renesas,gpio-rcar"; > + reg = <0 0xe6055000 0 0x50>; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&pfc 0 160 32>; > + #interrupt-cells = <2>; > + interrupt-controller; > + clocks = <&mstp9_clks R8A7795_CLK_GPIO5>; > + }; > + > + gpio6: gpio@e6055400 { > + compatible = "renesas,gpio-r8a7795", > + "renesas,gpio-rcar"; > + reg = <0 0xe6055400 0 0x50>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&pfc 0 192 32>; > + #interrupt-cells = <2>; > + interrupt-controller; > + clocks = <&mstp9_clks R8A7795_CLK_GPIO5>; This should say R8A7795_CLK_GPIO6... > + }; > + > + gpio7: gpio@e6055800 { > + compatible = "renesas,gpio-r8a7795", > + "renesas,gpio-rcar"; > + reg = <0 0xe6055800 0 0x50>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&pfc 0 224 32>; > + #interrupt-cells = <2>; > + interrupt-controller; > + clocks = <&mstp9_clks R8A7795_CLK_GPIO5>; ...and this R8A7795_CLK_GPIO7. CU Uli -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Aug 27, 2015 at 12:16:46PM +0200, Ulrich Hecht wrote:
> Thanks for the patch.
You are welcome.
I'll update my local copy with your suggestions regarding clocks.
I plan to replace that with a version you post whenever that occurs.
--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 9fba8be62025..a608eb92a172 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -52,6 +52,110 @@ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO0>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO1>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO2>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO3>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO4>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO5>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO5>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055800 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO5>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13