| Message ID | 1442254803-20043-5-git-send-email-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Sep 14, 2015 at 03:19:59PM -0300, Paulo Zanoni wrote: > BSpec says we shouldn't enable FBC on HSW/BDW when the pipe pixel rate > exceeds 95% of the core display clock. > > v2: > - HSW also needs the WA (Ville). > - Add the WA name (Ville). > - Use the current cdclk (Ville). > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_fbc.c | 10 ++++++++++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 1f02a5a..d22120f 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -949,6 +949,7 @@ struct i915_fbc { > FBC_ROTATION, /* rotation is not supported */ > FBC_IN_DBG_MASTER, /* kernel debugger is active */ > FBC_BAD_STRIDE, /* stride is not supported */ > + FBC_PIXEL_RATE, /* pixel rate is too big */ > } no_fbc_reason; > > bool (*fbc_enabled)(struct drm_i915_private *dev_priv); > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c > index 69726a7..1c4536a 100644 > --- a/drivers/gpu/drm/i915/intel_fbc.c > +++ b/drivers/gpu/drm/i915/intel_fbc.c > @@ -482,6 +482,8 @@ const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) > return "Kernel debugger is active"; > case FBC_BAD_STRIDE: > return "framebuffer stride not supported"; > + case FBC_PIXEL_RATE: > + return "pixel rate is too big"; > default: > MISSING_CASE(reason); > return "unknown reason"; > @@ -828,6 +830,14 @@ static void __intel_fbc_update(struct drm_i915_private *dev_priv) > goto out_disable; > } > > + /* WaFbcExceedCdClockThreshold:hsw,bdw */ > + if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && > + ilk_pipe_pixel_rate(intel_crtc->config) >= > + dev_priv->cdclk_freq * 95 / 100) { > + set_no_fbc_reason(dev_priv, FBC_PIXEL_RATE); > + goto out_disable; > + } > + > if (intel_fbc_setup_cfb(dev_priv, obj->base.size, > drm_format_plane_cpp(fb->pixel_format, 0))) { > set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL); > -- > 2.5.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1f02a5a..d22120f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -949,6 +949,7 @@ struct i915_fbc { FBC_ROTATION, /* rotation is not supported */ FBC_IN_DBG_MASTER, /* kernel debugger is active */ FBC_BAD_STRIDE, /* stride is not supported */ + FBC_PIXEL_RATE, /* pixel rate is too big */ } no_fbc_reason; bool (*fbc_enabled)(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 69726a7..1c4536a 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -482,6 +482,8 @@ const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) return "Kernel debugger is active"; case FBC_BAD_STRIDE: return "framebuffer stride not supported"; + case FBC_PIXEL_RATE: + return "pixel rate is too big"; default: MISSING_CASE(reason); return "unknown reason"; @@ -828,6 +830,14 @@ static void __intel_fbc_update(struct drm_i915_private *dev_priv) goto out_disable; } + /* WaFbcExceedCdClockThreshold:hsw,bdw */ + if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && + ilk_pipe_pixel_rate(intel_crtc->config) >= + dev_priv->cdclk_freq * 95 / 100) { + set_no_fbc_reason(dev_priv, FBC_PIXEL_RATE); + goto out_disable; + } + if (intel_fbc_setup_cfb(dev_priv, obj->base.size, drm_format_plane_cpp(fb->pixel_format, 0))) { set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL);
BSpec says we shouldn't enable FBC on HSW/BDW when the pipe pixel rate exceeds 95% of the core display clock. v2: - HSW also needs the WA (Ville). - Add the WA name (Ville). - Use the current cdclk (Ville). Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_fbc.c | 10 ++++++++++ 2 files changed, 11 insertions(+)