| Message ID | 1442033276-2191-5-git-send-email-sagar.a.kamble@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Looks good to me. Reviewed-by: Alex Dai <yu.dai@intel.com> On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote: > Cc: Tom O'Rourke <Tom.O'Rourke@intel.com> > Cc: Akash Goel <akash.goel@intel.com> > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 6e4818d..4d6bb6b 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4830,7 +4830,13 @@ static void gen9_enable_rc6(struct drm_device *dev) > I915_WRITE(GEN6_RC_CONTROL, 0); > > /* 2b: Program RC6 thresholds.*/ > - I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); > + > + /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ > + if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && > + (INTEL_REVID(dev) <= SKL_REVID_E0))) > + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); > + else > + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); > I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ > I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ > for_each_ring(ring, dev_priv, unused)
On Sat, Sep 12, 2015 at 10:17:53AM +0530, Sagar Arun Kamble wrote: > Cc: Tom O'Rourke <Tom.O'Rourke@intel.com> > Cc: Akash Goel <akash.goel@intel.com> > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 6e4818d..4d6bb6b 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4830,7 +4830,13 @@ static void gen9_enable_rc6(struct drm_device *dev) > I915_WRITE(GEN6_RC_CONTROL, 0); > > /* 2b: Program RC6 thresholds.*/ > - I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); > + > + /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ > + if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && > + (INTEL_REVID(dev) <= SKL_REVID_E0))) Same deal again. -Daniel > + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); > + else > + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); > I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ > I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ > for_each_ring(ring, dev_priv, unused) > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6e4818d..4d6bb6b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4830,7 +4830,13 @@ static void gen9_enable_rc6(struct drm_device *dev) I915_WRITE(GEN6_RC_CONTROL, 0); /* 2b: Program RC6 thresholds.*/ - I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); + + /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ + if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && + (INTEL_REVID(dev) <= SKL_REVID_E0))) + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); + else + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ for_each_ring(ring, dev_priv, unused)
Cc: Tom O'Rourke <Tom.O'Rourke@intel.com> Cc: Akash Goel <akash.goel@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)