| Message ID | 1443001002-5329-1-git-send-email-sagar.a.kamble@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
This change looks good and is necessary, but the commit message should have more detail. I would add: "When using RC6 timeout mode, the timeout value should be written to GEN6_RC6_THRESHOLD." With that, Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com> On Wed, Sep 23, 2015 at 03:06:42PM +0530, Sagar Arun Kamble wrote: > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index a878147..ebde43d 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4842,7 +4842,6 @@ static void gen9_enable_rc6(struct drm_device *dev) > for_each_ring(ring, dev_priv, unused) > I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); > I915_WRITE(GEN6_RC_SLEEP, 0); > - I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ > > /* 2c: Program Coarse Power Gating Policies. */ > I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); > @@ -4854,15 +4853,19 @@ static void gen9_enable_rc6(struct drm_device *dev) > DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? > "on" : "off"); > > + /* WaRsUseTimeoutMode */ > if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) || > - (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) > + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) { > + I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ > I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | > GEN7_RC_CTL_TO_MODE | > rc6_mask); > - else > + } else { > + I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ > I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | > GEN6_RC_CTL_EI_MODE(1) | > rc6_mask); > + } > > /* > * 3b: Enable Coarse Power Gating only when RC6 is enabled. > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a878147..ebde43d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4842,7 +4842,6 @@ static void gen9_enable_rc6(struct drm_device *dev) for_each_ring(ring, dev_priv, unused) I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); I915_WRITE(GEN6_RC_SLEEP, 0); - I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ /* 2c: Program Coarse Power Gating Policies. */ I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); @@ -4854,15 +4853,19 @@ static void gen9_enable_rc6(struct drm_device *dev) DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); + /* WaRsUseTimeoutMode */ if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) || - (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) { + I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | GEN7_RC_CTL_TO_MODE | rc6_mask); - else + } else { + I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask); + } /* * 3b: Enable Coarse Power Gating only when RC6 is enabled.
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)