| Message ID | 1440409251-11166-5-git-send-email-gabriel.fernandez@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 08/24, Gabriel Fernandez wrote: > Add support for new PLL-type for stih418 A9-PLL. > > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> > --- I assume this will go through arm-soc?
On 10/02/2015 09:32 PM, Stephen Boyd wrote: > On 08/24, Gabriel Fernandez wrote: >> Add support for new PLL-type for stih418 A9-PLL. >> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> >> --- > I assume this will go through arm-soc? > Yes, I will take it through STi tree. Thanks, Maxime
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index 148e177..ae6d997 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -44,7 +44,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"; clocks = <&clk_sysin>;
Add support for new PLL-type for stih418 A9-PLL. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- arch/arm/boot/dts/stih418-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)