| Message ID | 1444631169-19468-1-git-send-email-alim.akhtar@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 12.10.2015 15:26, Alim Akhtar wrote: > Since the merge of 2fad972 ("ARM: dts: Add mclk entry for Peach boards"), Please switch to longer SHA abbreviation: $ git config core.abbrev 12 > sound card detection is broken on peach boards and gives below errors: > > [ 3.630457] max98090 7-0010: MAX98091 REVID=0x51 > [ 3.634233] max98090 7-0010: use default 2.8v micbias > [ 3.640985] snow-audio sound: HiFi <-> 3830000.i2s mapping ok > [ 3.645307] max98090 7-0010: Invalid master clock frequency > [ 3.650824] snow-audio sound: ASoC: Peach-Pi-I2S-MAX98091 late_probe() failed: -22 > [ 3.658914] snow-audio sound: snd_soc_register_card failed (-22) > [ 3.664366] snow-audio: probe of sound failed with error -22 > > This patch adds missing assigned-clocks and assigned-clock-parents for > pmu_system_controller node which is used as "mclk" for audio codec. > > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> > Fixes: 2fad972 ("ARM: dts: Add mclk entry for Peach boards") > Cc: <stable@vger.kernel.org> > --- > arch/arm/boot/dts/exynos5420-peach-pit.dts | 5 +++++ > arch/arm/boot/dts/exynos5800-peach-pi.dts | 5 +++++ > 2 files changed, 10 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts > index 8f4d76c..525a93a 100644 > --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts > +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts > @@ -1056,5 +1056,10 @@ > timeout-sec = <32>; > }; > > +&pmu_system_controller { Please put the node in alphabetical order. > + assigned-clocks = <&pmu_system_controller 0>; > + assigned-clock-parents = <&clock CLK_FIN_PLL>; I might be missing something here but isn't the first clock of pmu_system_controller already a CLK_FIN_PLL? So you are reparenting the FIN_PLL to FIN_PLL? In the same time there is doubled space character after '='. > +}; > + > #include "cros-ec-keyboard.dtsi" > #include "cros-adc-thermistors.dtsi" > diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts > index 7d5b386..411de8f 100644 > --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts > +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts > @@ -1019,5 +1019,10 @@ > timeout-sec = <32>; > }; > > +&pmu_system_controller { > + assigned-clocks = <&pmu_system_controller 0>; > + assigned-clock-parents = <&clock CLK_FIN_PLL>; Ditto. Best regards, Krzysztof > +}; > + > #include "cros-ec-keyboard.dtsi" > #include "cros-adc-thermistors.dtsi" >
On 12/10/15 08:47, Krzysztof Kozlowski wrote: >> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts >> > index 8f4d76c..525a93a 100644 >> > --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts >> > +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts >> > @@ -1056,5 +1056,10 @@ >> > timeout-sec = <32>; >> > }; >> > >> > +&pmu_system_controller { > > Please put the node in alphabetical order. > >> > + assigned-clocks = <&pmu_system_controller 0>; >> > + assigned-clock-parents = <&clock CLK_FIN_PLL>; > > I might be missing something here but isn't the first clock of > pmu_system_controller already a CLK_FIN_PLL? So you are reparenting the > FIN_PLL to FIN_PLL? No, it's not, the first PMU consumer clock is indeed CLK_FIN_PLL, but pmu_system_controller is also a clock provider. The first output clock of pmu_system_controller is CLKOUT, it's a composite mux and gate clock (registered in drivers/clk/samsung /clk-exynos-clkout.c). So the above dts change is selecting an external oscillator input of the CLKOUT mux, i.e. it will route 24 MHz clock signal from the external oscillator to the CLKOUT output pin, to which audio CODEC is connected on peach-pit AFAICS.
Hi Sylwester, On 10/12/2015 02:48 PM, Sylwester Nawrocki wrote: > On 12/10/15 08:47, Krzysztof Kozlowski wrote: >>> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts >>>> index 8f4d76c..525a93a 100644 >>>> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts >>>> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts >>>> @@ -1056,5 +1056,10 @@ >>>> timeout-sec = <32>; >>>> }; >>>> >>>> +&pmu_system_controller { >> >> Please put the node in alphabetical order. >> >>>> + assigned-clocks = <&pmu_system_controller 0>; >>>> + assigned-clock-parents = <&clock CLK_FIN_PLL>; >> >> I might be missing something here but isn't the first clock of >> pmu_system_controller already a CLK_FIN_PLL? So you are reparenting the >> FIN_PLL to FIN_PLL? > > No, it's not, the first PMU consumer clock is indeed CLK_FIN_PLL, > but pmu_system_controller is also a clock provider. The first output > clock of pmu_system_controller is CLKOUT, it's a composite mux and > gate clock (registered in drivers/clk/samsung /clk-exynos-clkout.c). > So the above dts change is selecting an external oscillator input of > the CLKOUT mux, i.e. it will route 24 MHz clock signal from the external > oscillator to the CLKOUT output pin, to which audio CODEC is connected > on peach-pit AFAICS. > Thanks for your explanation, indeed master clock of codec is connected to XCLKOUT on peach boards. Will send v2 addressing Kezysztof's other comments. Regards, Alim
Hello Kezysztof Thanks for your review. On 10/12/2015 12:17 PM, Krzysztof Kozlowski wrote: > On 12.10.2015 15:26, Alim Akhtar wrote: >> Since the merge of 2fad972 ("ARM: dts: Add mclk entry for Peach boards"), > > Please switch to longer SHA abbreviation: > $ git config core.abbrev 12 > ok, will do thanks >> sound card detection is broken on peach boards and gives below errors: >> >> [ 3.630457] max98090 7-0010: MAX98091 REVID=0x51 >> [ 3.634233] max98090 7-0010: use default 2.8v micbias >> [ 3.640985] snow-audio sound: HiFi <-> 3830000.i2s mapping ok >> [ 3.645307] max98090 7-0010: Invalid master clock frequency >> [ 3.650824] snow-audio sound: ASoC: Peach-Pi-I2S-MAX98091 late_probe() failed: -22 >> [ 3.658914] snow-audio sound: snd_soc_register_card failed (-22) >> [ 3.664366] snow-audio: probe of sound failed with error -22 >> >> This patch adds missing assigned-clocks and assigned-clock-parents for >> pmu_system_controller node which is used as "mclk" for audio codec. >> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> >> Fixes: 2fad972 ("ARM: dts: Add mclk entry for Peach boards") >> Cc: <stable@vger.kernel.org> >> --- >> arch/arm/boot/dts/exynos5420-peach-pit.dts | 5 +++++ >> arch/arm/boot/dts/exynos5800-peach-pi.dts | 5 +++++ >> 2 files changed, 10 insertions(+) >> >> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts >> index 8f4d76c..525a93a 100644 >> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts >> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts >> @@ -1056,5 +1056,10 @@ >> timeout-sec = <32>; >> }; >> >> +&pmu_system_controller { > > Please put the node in alphabetical order. > ok >> + assigned-clocks = <&pmu_system_controller 0>; >> + assigned-clock-parents = <&clock CLK_FIN_PLL>; > > I might be missing something here but isn't the first clock of > pmu_system_controller already a CLK_FIN_PLL? So you are reparenting the > FIN_PLL to FIN_PLL? > > In the same time there is doubled space character after '='. > will remove >> +}; >> + >> #include "cros-ec-keyboard.dtsi" >> #include "cros-adc-thermistors.dtsi" >> diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts >> index 7d5b386..411de8f 100644 >> --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts >> +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts >> @@ -1019,5 +1019,10 @@ >> timeout-sec = <32>; >> }; >> >> +&pmu_system_controller { >> + assigned-clocks = <&pmu_system_controller 0>; >> + assigned-clock-parents = <&clock CLK_FIN_PLL>; > > Ditto. > > Best regards, > Krzysztof > > >> +}; >> + >> #include "cros-ec-keyboard.dtsi" >> #include "cros-adc-thermistors.dtsi" >> > >
W dniu 12.10.2015 o 18:18, Sylwester Nawrocki pisze: > On 12/10/15 08:47, Krzysztof Kozlowski wrote: >>> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts >>>> index 8f4d76c..525a93a 100644 >>>> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts >>>> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts >>>> @@ -1056,5 +1056,10 @@ >>>> timeout-sec = <32>; >>>> }; >>>> >>>> +&pmu_system_controller { >> >> Please put the node in alphabetical order. >> >>>> + assigned-clocks = <&pmu_system_controller 0>; >>>> + assigned-clock-parents = <&clock CLK_FIN_PLL>; >> >> I might be missing something here but isn't the first clock of >> pmu_system_controller already a CLK_FIN_PLL? So you are reparenting the >> FIN_PLL to FIN_PLL? > > No, it's not, the first PMU consumer clock is indeed CLK_FIN_PLL, > but pmu_system_controller is also a clock provider. Oh yes, indeed it is. Thanks for pointing me in right direction. Best regards, Krzysztof > The first output > clock of pmu_system_controller is CLKOUT, it's a composite mux and > gate clock (registered in drivers/clk/samsung /clk-exynos-clkout.c). > So the above dts change is selecting an external oscillator input of > the CLKOUT mux, i.e. it will route 24 MHz clock signal from the external > oscillator to the CLKOUT output pin, to which audio CODEC is connected > on peach-pit AFAICS.
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 8f4d76c..525a93a 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -1056,5 +1056,10 @@ timeout-sec = <32>; }; +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_FIN_PLL>; +}; + #include "cros-ec-keyboard.dtsi" #include "cros-adc-thermistors.dtsi" diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 7d5b386..411de8f 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -1019,5 +1019,10 @@ timeout-sec = <32>; }; +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_FIN_PLL>; +}; + #include "cros-ec-keyboard.dtsi" #include "cros-adc-thermistors.dtsi"
Since the merge of 2fad972 ("ARM: dts: Add mclk entry for Peach boards"), sound card detection is broken on peach boards and gives below errors: [ 3.630457] max98090 7-0010: MAX98091 REVID=0x51 [ 3.634233] max98090 7-0010: use default 2.8v micbias [ 3.640985] snow-audio sound: HiFi <-> 3830000.i2s mapping ok [ 3.645307] max98090 7-0010: Invalid master clock frequency [ 3.650824] snow-audio sound: ASoC: Peach-Pi-I2S-MAX98091 late_probe() failed: -22 [ 3.658914] snow-audio sound: snd_soc_register_card failed (-22) [ 3.664366] snow-audio: probe of sound failed with error -22 This patch adds missing assigned-clocks and assigned-clock-parents for pmu_system_controller node which is used as "mclk" for audio codec. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Fixes: 2fad972 ("ARM: dts: Add mclk entry for Peach boards") Cc: <stable@vger.kernel.org> --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 5 +++++ arch/arm/boot/dts/exynos5800-peach-pi.dts | 5 +++++ 2 files changed, 10 insertions(+)