| Message ID | 1444979960-24100-5-git-send-email-Minghuan.Lian@freescale.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
On Fri, Oct 16, 2015 at 03:19:19PM +0800, Minghuan Lian wrote: > Both LS1043a and LS2080a are based on ARMv8 64-bit architecture > and have similar PCIe implementation. LUT is added to controller. > The patch removes the necessary fields from struct ls_pcie. > > Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> > --- > This patch is based on v4.3-rc4 and [PATCH v10 3/6] > PCI: designware: Add ARM64 support. > > change log > v4: > 1. split to 6 patches. > 2. use ARCH_LAYERSCAPE instead of ARM64 > > v3: > 1. Use 8 or 16 bit access function to simplify code > 2. Add ls_add_pcie_port in accordance with other DesignWare-based drivers > > v2: > 1. Rename ls2085a to ls2080a > 2. Add ls_pcie_msi_host_init() > > drivers/pci/host/Kconfig | 2 +- > drivers/pci/host/pci-layerscape.c | 72 +++++++++++++++++++++++++++++++++++---- > 2 files changed, 67 insertions(+), 7 deletions(-) > > diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig > index ae873be..8eb09ea 100644 > --- a/drivers/pci/host/Kconfig > +++ b/drivers/pci/host/Kconfig > @@ -105,7 +105,7 @@ config PCI_XGENE_MSI > > config PCI_LAYERSCAPE > bool "Freescale Layerscape PCIe controller" > - depends on OF && ARM > + depends on OF && (ARM || ARCH_LAYERSCAPE) > select PCIE_DW > select MFD_SYSCON > help > diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c > index 891e504..c53692a 100644 > --- a/drivers/pci/host/pci-layerscape.c > +++ b/drivers/pci/host/pci-layerscape.c > @@ -31,23 +31,26 @@ > #define LTSSM_STATE_MASK 0x3f > #define LTSSM_PCIE_L0 0x11 /* L0 state */ > > -/* Symbol Timer Register and Filter Mask Register 1 */ > -#define PCIE_STRFMR1 0x71c > +/* PEX Internal Configuration Registers */ > +#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ > +#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ > + > +/* PEX LUT registers */ > +#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */ > > struct ls_pcie_drvdata { > + u32 lut_offset; > + u32 ltssm_shift; > struct pcie_host_ops *ops; > }; > > struct ls_pcie { > - struct list_head node; > - struct device *dev; > - struct pci_bus *bus; These fields look unused and unrelated to LS1043a and LS2080a. I split their removal into a separate patch. > void __iomem *dbi; > + void __iomem *lut; > struct regmap *scfg; > struct pcie_port pp; > const struct ls_pcie_drvdata *drvdata; > int index; > - int msi_irq; > }; > > #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp) > @@ -62,6 +65,18 @@ static bool ls_pcie_is_bridge(struct ls_pcie *pcie) > return header_type == PCI_HEADER_TYPE_BRIDGE; > } > > +/* Clear multi-function bit */ > +static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) > +{ > + iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE); > +} > + > +/* Fix class value */ > +static void ls_pcie_fix_class(struct ls_pcie *pcie) > +{ > + iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); > +} > + > static int ls1021_pcie_link_up(struct pcie_port *pp) > { > u32 state; > @@ -110,17 +125,61 @@ static void ls1021_pcie_host_init(struct pcie_port *pp) > iowrite32(val, pcie->dbi + PCIE_STRFMR1); > } > > +static int ls_pcie_link_up(struct pcie_port *pp) > +{ > + struct ls_pcie *pcie = to_ls_pcie(pp); > + u32 state; > + > + state = (ioread32(pcie->lut + PCIE_LUT_DBG) >> > + pcie->drvdata->ltssm_shift) & > + LTSSM_STATE_MASK; > + > + if (state < LTSSM_PCIE_L0) > + return 0; > + > + return 1; > +} > + > +static void ls_pcie_host_init(struct pcie_port *pp) > +{ > + struct ls_pcie *pcie = to_ls_pcie(pp); > + > + iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN); > + ls_pcie_fix_class(pcie); > + ls_pcie_clear_multifunction(pcie); > + iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN); > +} > + > static struct pcie_host_ops ls1021_pcie_host_ops = { > .link_up = ls1021_pcie_link_up, > .host_init = ls1021_pcie_host_init, > }; > > +static struct pcie_host_ops ls_pcie_host_ops = { > + .link_up = ls_pcie_link_up, > + .host_init = ls_pcie_host_init, > +}; > + > static struct ls_pcie_drvdata ls1021_drvdata = { > .ops = &ls1021_pcie_host_ops, > }; > > +static struct ls_pcie_drvdata ls1043_drvdata = { > + .lut_offset = 0x10000, > + .ltssm_shift = 24, > + .ops = &ls_pcie_host_ops, > +}; > + > +static struct ls_pcie_drvdata ls2080_drvdata = { > + .lut_offset = 0x80000, > + .ltssm_shift = 0, > + .ops = &ls_pcie_host_ops, > +}; > + > static const struct of_device_id ls_pcie_of_match[] = { > { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, > + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, > + { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, > { }, > }; > MODULE_DEVICE_TABLE(of, ls_pcie_of_match); > @@ -167,6 +226,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev) > } > > pcie->drvdata = match->data; > + pcie->lut = pcie->dbi + pcie->drvdata->lut_offset; > > if (!ls_pcie_is_bridge(pcie)) > return -ENODEV; > -- > 1.9.1 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[+cc Fabio, Lucas] Hi Minghuan, On Fri, Oct 16, 2015 at 03:19:19PM +0800, Minghuan Lian wrote: > Both LS1043a and LS2080a are based on ARMv8 64-bit architecture > and have similar PCIe implementation. LUT is added to controller. > The patch removes the necessary fields from struct ls_pcie. > > Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> > --- > This patch is based on v4.3-rc4 and [PATCH v10 3/6] > PCI: designware: Add ARM64 support. > > change log > v4: > 1. split to 6 patches. > 2. use ARCH_LAYERSCAPE instead of ARM64 > > v3: > 1. Use 8 or 16 bit access function to simplify code > 2. Add ls_add_pcie_port in accordance with other DesignWare-based drivers > > v2: > 1. Rename ls2085a to ls2080a > 2. Add ls_pcie_msi_host_init() > > drivers/pci/host/Kconfig | 2 +- > drivers/pci/host/pci-layerscape.c | 72 +++++++++++++++++++++++++++++++++++---- > 2 files changed, 67 insertions(+), 7 deletions(-) > > diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig > index ae873be..8eb09ea 100644 > --- a/drivers/pci/host/Kconfig > +++ b/drivers/pci/host/Kconfig > @@ -105,7 +105,7 @@ config PCI_XGENE_MSI > > config PCI_LAYERSCAPE > bool "Freescale Layerscape PCIe controller" > - depends on OF && ARM > + depends on OF && (ARM || ARCH_LAYERSCAPE) > select PCIE_DW > select MFD_SYSCON > help > diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c > index 891e504..c53692a 100644 > --- a/drivers/pci/host/pci-layerscape.c > +++ b/drivers/pci/host/pci-layerscape.c > @@ -31,23 +31,26 @@ > #define LTSSM_STATE_MASK 0x3f BTW, not related to *this* patch, but does LTSSM_STATE_MASK really need to be 0x3f (6 bits), or could it be 0x1f (5 bits)? I'd like to include Layerscape in the LTSSM_STATE_MASK cleanup done by Fabio: https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=pci/host-designware&id=4788fe6ebf4594c9a95b620cbff05147c8504823 I don't have specs for any of these devices, so I don't know if this is really something that can vary between the different DesignWare-based devices, or if they all should use a mask of 0x1f. Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, Oct 21, 2015 at 4:36 PM, Bjorn Helgaas <helgaas@kernel.org> wrote: > On Fri, Oct 16, 2015 at 03:19:19PM +0800, Minghuan Lian wrote: >> Both LS1043a and LS2080a are based on ARMv8 64-bit architecture >> and have similar PCIe implementation. LUT is added to controller. >> The patch removes the necessary fields from struct ls_pcie. >> >> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> >> --- >> This patch is based on v4.3-rc4 and [PATCH v10 3/6] >> PCI: designware: Add ARM64 support. Hi Bjorn, Are you also applying this patch https://patchwork.ozlabs.org/patch/531184/ in this merge windows? Because the new hardware can only work with the generic ARM64 support added in the designware pcie driver. Regards, Leo -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Leo, On Thu, Oct 22, 2015 at 12:38:48PM -0500, Li Yang wrote: > On Wed, Oct 21, 2015 at 4:36 PM, Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Fri, Oct 16, 2015 at 03:19:19PM +0800, Minghuan Lian wrote: > >> Both LS1043a and LS2080a are based on ARMv8 64-bit architecture > >> and have similar PCIe implementation. LUT is added to controller. > >> The patch removes the necessary fields from struct ls_pcie. > >> > >> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> > >> --- > >> This patch is based on v4.3-rc4 and [PATCH v10 3/6] > >> PCI: designware: Add ARM64 support. > > Hi Bjorn, > > Are you also applying this patch > https://patchwork.ozlabs.org/patch/531184/ in this merge windows? > Because the new hardware can only work with the generic ARM64 support > added in the designware pcie driver. I'm reviewing that patch right now, and I do hope to apply it for v4.4. There was no cover letter for this series (Minghuan's Layerscape v4 series), and I didn't see any mention of dependencies, so I applied it on top of v4.3-rc1. Is that the wrong thing to do? If it depends on the Zhou's v11 series, I can hold the Layerscape branch until after that. Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Oct 22, 2015 at 1:08 PM, Bjorn Helgaas <helgaas@kernel.org> wrote: > Hi Leo, > > On Thu, Oct 22, 2015 at 12:38:48PM -0500, Li Yang wrote: >> On Wed, Oct 21, 2015 at 4:36 PM, Bjorn Helgaas <helgaas@kernel.org> wrote: >> > On Fri, Oct 16, 2015 at 03:19:19PM +0800, Minghuan Lian wrote: >> >> Both LS1043a and LS2080a are based on ARMv8 64-bit architecture >> >> and have similar PCIe implementation. LUT is added to controller. >> >> The patch removes the necessary fields from struct ls_pcie. >> >> >> >> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> >> >> --- >> >> This patch is based on v4.3-rc4 and [PATCH v10 3/6] >> >> PCI: designware: Add ARM64 support. >> >> Hi Bjorn, >> >> Are you also applying this patch >> https://patchwork.ozlabs.org/patch/531184/ in this merge windows? >> Because the new hardware can only work with the generic ARM64 support >> added in the designware pcie driver. > > I'm reviewing that patch right now, and I do hope to apply it for > v4.4. > > There was no cover letter for this series (Minghuan's Layerscape v4 > series), and I didn't see any mention of dependencies, so I applied it > on top of v4.3-rc1. Is that the wrong thing to do? If it depends on > the Zhou's v11 series, I can hold the Layerscape branch until after > that. I don't know if this patch will break anything without Zhou's patch. But the new hardware mentioned in the description will not be working without the dependent patch. We should hold this patch until after the generic change is merged. Minghuan, are there any bug fixing patch in the series that need to be merged earlier? Regards, Leo -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Oct 22, 2015 at 1:08 PM, Bjorn Helgaas <helgaas@kernel.org> wrote: > Hi Leo, > > On Thu, Oct 22, 2015 at 12:38:48PM -0500, Li Yang wrote: >> On Wed, Oct 21, 2015 at 4:36 PM, Bjorn Helgaas <helgaas@kernel.org> wrote: >> > On Fri, Oct 16, 2015 at 03:19:19PM +0800, Minghuan Lian wrote: >> >> Both LS1043a and LS2080a are based on ARMv8 64-bit architecture >> >> and have similar PCIe implementation. LUT is added to controller. >> >> The patch removes the necessary fields from struct ls_pcie. >> >> >> >> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> >> >> --- >> >> This patch is based on v4.3-rc4 and [PATCH v10 3/6] >> >> PCI: designware: Add ARM64 support. >> >> Hi Bjorn, >> >> Are you also applying this patch >> https://patchwork.ozlabs.org/patch/531184/ in this merge windows? >> Because the new hardware can only work with the generic ARM64 support >> added in the designware pcie driver. > > I'm reviewing that patch right now, and I do hope to apply it for > v4.4. > > There was no cover letter for this series (Minghuan's Layerscape v4 > series), and I didn't see any mention of dependencies, so I applied it > on top of v4.3-rc1. Is that the wrong thing to do? If it depends on > the Zhou's v11 series, I can hold the Layerscape branch until after > that. I noticed that you have merged Zhou's latest patch. Probably you can also merge the Layerscape branch now. Regards, Leo -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Nov 02, 2015 at 03:08:04PM -0600, Li Yang wrote: > On Thu, Oct 22, 2015 at 1:08 PM, Bjorn Helgaas <helgaas@kernel.org> wrote: > > Hi Leo, > > > > On Thu, Oct 22, 2015 at 12:38:48PM -0500, Li Yang wrote: > >> On Wed, Oct 21, 2015 at 4:36 PM, Bjorn Helgaas <helgaas@kernel.org> wrote: > >> > On Fri, Oct 16, 2015 at 03:19:19PM +0800, Minghuan Lian wrote: > >> >> Both LS1043a and LS2080a are based on ARMv8 64-bit architecture > >> >> and have similar PCIe implementation. LUT is added to controller. > >> >> The patch removes the necessary fields from struct ls_pcie. > >> >> > >> >> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> > >> >> --- > >> >> This patch is based on v4.3-rc4 and [PATCH v10 3/6] > >> >> PCI: designware: Add ARM64 support. > >> > >> Hi Bjorn, > >> > >> Are you also applying this patch > >> https://patchwork.ozlabs.org/patch/531184/ in this merge windows? > >> Because the new hardware can only work with the generic ARM64 support > >> added in the designware pcie driver. > > > > I'm reviewing that patch right now, and I do hope to apply it for > > v4.4. > > > > There was no cover letter for this series (Minghuan's Layerscape v4 > > series), and I didn't see any mention of dependencies, so I applied it > > on top of v4.3-rc1. Is that the wrong thing to do? If it depends on > > the Zhou's v11 series, I can hold the Layerscape branch until after > > that. > > I noticed that you have merged Zhou's latest patch. Probably you can > also merge the Layerscape branch now. That's my intention. Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index ae873be..8eb09ea 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -105,7 +105,7 @@ config PCI_XGENE_MSI config PCI_LAYERSCAPE bool "Freescale Layerscape PCIe controller" - depends on OF && ARM + depends on OF && (ARM || ARCH_LAYERSCAPE) select PCIE_DW select MFD_SYSCON help diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 891e504..c53692a 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -31,23 +31,26 @@ #define LTSSM_STATE_MASK 0x3f #define LTSSM_PCIE_L0 0x11 /* L0 state */ -/* Symbol Timer Register and Filter Mask Register 1 */ -#define PCIE_STRFMR1 0x71c +/* PEX Internal Configuration Registers */ +#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ +#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ + +/* PEX LUT registers */ +#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */ struct ls_pcie_drvdata { + u32 lut_offset; + u32 ltssm_shift; struct pcie_host_ops *ops; }; struct ls_pcie { - struct list_head node; - struct device *dev; - struct pci_bus *bus; void __iomem *dbi; + void __iomem *lut; struct regmap *scfg; struct pcie_port pp; const struct ls_pcie_drvdata *drvdata; int index; - int msi_irq; }; #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp) @@ -62,6 +65,18 @@ static bool ls_pcie_is_bridge(struct ls_pcie *pcie) return header_type == PCI_HEADER_TYPE_BRIDGE; } +/* Clear multi-function bit */ +static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) +{ + iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE); +} + +/* Fix class value */ +static void ls_pcie_fix_class(struct ls_pcie *pcie) +{ + iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); +} + static int ls1021_pcie_link_up(struct pcie_port *pp) { u32 state; @@ -110,17 +125,61 @@ static void ls1021_pcie_host_init(struct pcie_port *pp) iowrite32(val, pcie->dbi + PCIE_STRFMR1); } +static int ls_pcie_link_up(struct pcie_port *pp) +{ + struct ls_pcie *pcie = to_ls_pcie(pp); + u32 state; + + state = (ioread32(pcie->lut + PCIE_LUT_DBG) >> + pcie->drvdata->ltssm_shift) & + LTSSM_STATE_MASK; + + if (state < LTSSM_PCIE_L0) + return 0; + + return 1; +} + +static void ls_pcie_host_init(struct pcie_port *pp) +{ + struct ls_pcie *pcie = to_ls_pcie(pp); + + iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN); + ls_pcie_fix_class(pcie); + ls_pcie_clear_multifunction(pcie); + iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN); +} + static struct pcie_host_ops ls1021_pcie_host_ops = { .link_up = ls1021_pcie_link_up, .host_init = ls1021_pcie_host_init, }; +static struct pcie_host_ops ls_pcie_host_ops = { + .link_up = ls_pcie_link_up, + .host_init = ls_pcie_host_init, +}; + static struct ls_pcie_drvdata ls1021_drvdata = { .ops = &ls1021_pcie_host_ops, }; +static struct ls_pcie_drvdata ls1043_drvdata = { + .lut_offset = 0x10000, + .ltssm_shift = 24, + .ops = &ls_pcie_host_ops, +}; + +static struct ls_pcie_drvdata ls2080_drvdata = { + .lut_offset = 0x80000, + .ltssm_shift = 0, + .ops = &ls_pcie_host_ops, +}; + static const struct of_device_id ls_pcie_of_match[] = { { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, + { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, { }, }; MODULE_DEVICE_TABLE(of, ls_pcie_of_match); @@ -167,6 +226,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev) } pcie->drvdata = match->data; + pcie->lut = pcie->dbi + pcie->drvdata->lut_offset; if (!ls_pcie_is_bridge(pcie)) return -ENODEV;
Both LS1043a and LS2080a are based on ARMv8 64-bit architecture and have similar PCIe implementation. LUT is added to controller. The patch removes the necessary fields from struct ls_pcie. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> --- This patch is based on v4.3-rc4 and [PATCH v10 3/6] PCI: designware: Add ARM64 support. change log v4: 1. split to 6 patches. 2. use ARCH_LAYERSCAPE instead of ARM64 v3: 1. Use 8 or 16 bit access function to simplify code 2. Add ls_add_pcie_port in accordance with other DesignWare-based drivers v2: 1. Rename ls2085a to ls2080a 2. Add ls_pcie_msi_host_init() drivers/pci/host/Kconfig | 2 +- drivers/pci/host/pci-layerscape.c | 72 +++++++++++++++++++++++++++++++++++---- 2 files changed, 67 insertions(+), 7 deletions(-)