| Message ID | 56377ED5.4070203@sigmadesigns.com (mailing list archive) |
|---|---|
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Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes: > This device tree was tested on a Sigma Designs SMP8758 Vantage-1172 > development board. > > Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> > --- > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/tango4-common.dtsi | 121 ++++++++++++++++++++++++++++++ > arch/arm/boot/dts/tango4-smp8758.dtsi | 30 ++++++++ > arch/arm/boot/dts/tango4-vantage-1172.dts | 24 ++++++ > 4 files changed, 177 insertions(+) > create mode 100644 arch/arm/boot/dts/tango4-common.dtsi > create mode 100644 arch/arm/boot/dts/tango4-smp8758.dtsi > create mode 100644 arch/arm/boot/dts/tango4-vantage-1172.dts > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 246473a244f6..2499295051d5 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -605,6 +605,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ > dtb-$(CONFIG_MACH_SUN9I) += \ > sun9i-a80-optimus.dtb \ > sun9i-a80-cubieboard4.dtb > +dtb-$(CONFIG_ARCH_TANGOX) += \ > + tango4-vantage-1172.dtb > dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ > tegra20-harmony.dtb \ > tegra20-iris-512.dtb \ > diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi > new file mode 100644 > index 000000000000..90e9a6e736ae > --- /dev/null > +++ b/arch/arm/boot/dts/tango4-common.dtsi > @@ -0,0 +1,121 @@ > +/* > + * Derived from Mans Rullgard's Tango3 DT > + * https://github.com/mansr/linux-tangox > + */ Why don't you take the tango4 one from the same repo? > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + > + clocks { > + ranges; > + #address-cells = <1>; > + #size-cells = <1>; > + > + xtal: xtal { > + compatible = "fixed-clock"; > + clock-frequency = <27000000>; > + #clock-cells = <0>; > + }; > + > + clkgen: clkgen@10000 { > + compatible = "sigma,tango4-clkgen"; > + reg = <0x10000 0x40>; > + clocks = <&xtal>; > + clock-output-names = "cpuclk", "sysclk"; > + #clock-cells = <1>; > + }; There are about a dozen more clocks that will be needed eventually. Do you have a plan for how to add them? (My driver already has support for most of them.) > + }; > + > + gic: interrupt-controller@20001000 { > + compatible = "arm,cortex-a9-gic"; > + interrupt-controller; > + #interrupt-cells = <3>; > + reg = <0x20001000 0x1000>, <0x20000100 0x0100>; > + }; > + > + l2cc: l2-cache-controller@20100000 { > + compatible = "arm,pl310-cache"; > + reg = <0x20100000 0x1000>; > + cache-level = <2>; > + cache-unified; > + }; > + > + periphclk: periphclk { Why is this not in the clocks block above? > + compatible = "fixed-factor-clock"; > + clocks = <&clkgen 0>; > + clock-mult = <1>; > + clock-div = <2>; Some Sigma source code I found on the Internet uses a divisor of 3. Which is correct? > + #clock-cells = <0>; > + }; > + > + twd-timer@20000600 { > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0x20000600 0x10>; > + interrupts = <GIC_PPI 13 0xf04>; > + interrupt-parent = <&gic>; > + clocks = <&periphclk>; > + always-on; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; Put interrupt-parent = <&irq0> here and save repeating it for each device. > + tick-counter@10048 { > + compatible = "sigma,tick-counter"; This compatible name is too vague. What if the next Sigma chip has a completely different counter? > + reg = <0x10048 0x4>; > + clocks = <&xtal>; > + }; > + > + uart: serial@10700 { > + compatible = "ralink,rt2880-uart"; > + reg = <0x10700 0x30>; > + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-parent = <&irq0>; > + clock-frequency = <7372800>; > + reg-shift = <2>; > + }; > + > + eth0: ethernet@26000 { > + reg = <0x26000 0x800>; > + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-parent = <&irq0>; > + clocks = <&clkgen 1>; > + }; Missing compatible string. > + intc: interrupt-controller@6e000 { > + reg = <0x6e000 0x400>; > + ranges = <0 0x6e000 0x400>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + #address-cells = <1>; > + #size-cells = <1>; Missing compatible string. > + irq0: irq0@6e000 { The node name should be interrupt-controller@000, similarly below. > + reg = <0x000 0x100>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + irq1: irq1@6e100 { > + reg = <0x100 0x100>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + irq2: irq2@6e300 { > + reg = <0x300 0x100>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + }; > +}; > diff --git a/arch/arm/boot/dts/tango4-smp8758.dtsi b/arch/arm/boot/dts/tango4-smp8758.dtsi > new file mode 100644 > index 000000000000..4eb23a12e27f > --- /dev/null > +++ b/arch/arm/boot/dts/tango4-smp8758.dtsi > @@ -0,0 +1,30 @@ > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "sigma,tango4-smp"; This enable-method is too vague. The next chip might be different. > + cpu0: cpu@0 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + reg = <0>; > + }; > + > + cpu1: cpu@1 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + reg = <1>; > + }; > + }; > + > + pmu { > + compatible = "arm,cortex-a9-pmu"; > + interrupt-affinity = <&cpu0>, <&cpu1>; > + interrupt-parent = <&gic>; > + interrupts = > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > + }; > +}; The device tree should mention the SCU. > diff --git a/arch/arm/boot/dts/tango4-vantage-1172.dts b/arch/arm/boot/dts/tango4-vantage-1172.dts > new file mode 100644 > index 000000000000..22de3624ed97 > --- /dev/null > +++ b/arch/arm/boot/dts/tango4-vantage-1172.dts > @@ -0,0 +1,24 @@ > +/dts-v1/; > + > +#include "tango4-smp8758.dtsi" > +#include "tango4-common.dtsi" > + > +/ { > + model = "Sigma Designs SMP8758 Vantage-1172 dev board"; > + compatible = "sigma,vantage-1172", "sigma,smp8758", "sigma,tango4"; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x80000000>; /* 2 GB */ > + }; > +}; > + > +ð0 { > + compatible = "sigma,smp8758-ethernet", "sigma,smp8734-ethernet", "sigma,smp8642-ethernet", "aurora,nb8800"; It's odd to specify the compatible string here. It certainly won't change between different boards using the same chip. Also, in the latest version of my driver, tango3 and tango4 are unfortunately not compatible. The incompatibility only showed up once I enabled the L2 cache. I don't know quite what's going on. > + phy-connection-type = "rgmii"; > + max-speed = <1000>; You should have a node for the PHY here. > +}; > + > +&intc { > + compatible = "sigma,smp8758-intc", "sigma,smp8642-intc"; Wrong place for the compatible string. > +};
On 02/11/2015 17:01, Måns Rullgård wrote: > There are about a dozen more clocks that will be needed eventually. Do > you have a plan for how to add them? (My driver already has support for > most of them.) Can you tell me which clocks (for which device) you've needed on the smp8759? >> + periphclk: periphclk { > > Why is this not in the clocks block above? It was something the clk maintainer said that made me move it, but I can't find it anymore. I can move it back if that's the consensus. >> + compatible = "fixed-factor-clock"; >> + clocks = <&clkgen 0>; >> + clock-mult = <1>; >> + clock-div = <2>; > > Some Sigma source code I found on the Internet uses a divisor of 3. > Which is correct? I was told 2. >> + soc { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; > > Put interrupt-parent = <&irq0> here and save repeating it for each device. Each device can have either irq0, irq1, or irq2 as the parent, right? The old code tried to do IRQ load-balancing "by hand". I had the vague idea that I would set some devices to irq0, others to irq1, and have irq_i interrupt CPU_i. Does that make no sense? >> + tick-counter@10048 { >> + compatible = "sigma,tick-counter"; > > This compatible name is too vague. What if the next Sigma chip has a > completely different counter? When this happens, I could switch to the generic method you've proposed. >> + eth0: ethernet@26000 { >> + reg = <0x26000 0x800>; >> + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-parent = <&irq0>; >> + clocks = <&clkgen 1>; >> + }; > > Missing compatible string. It's not missing, it's elsewhere. (But maybe I did it wrong.) >> + intc: interrupt-controller@6e000 { >> + reg = <0x6e000 0x400>; >> + ranges = <0 0x6e000 0x400>; >> + interrupt-parent = <&gic>; >> + interrupt-controller; >> + #address-cells = <1>; >> + #size-cells = <1>; > > Missing compatible string. > >> + irq0: irq0@6e000 { > > The node name should be interrupt-controller@000, similarly below. <confused> I changed that a long time ago, and Arnd didn't flag it. I'll put whatever the arm-soc maintainers say. >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + enable-method = "sigma,tango4-smp"; > > This enable-method is too vague. The next chip might be different. What string do you propose? What if I don't expect any other tango4 chip? > The device tree should mention the SCU. I left it out because I thought it was the firmware's responsibility. I will double-check with the firmware author. >> +ð0 { >> + compatible = "sigma,smp8758-ethernet", "sigma,smp8734-ethernet", "sigma,smp8642-ethernet", "aurora,nb8800"; > > It's odd to specify the compatible string here. It certainly won't > change between different boards using the same chip. Also, in the > latest version of my driver, tango3 and tango4 are unfortunately not > compatible. The incompatibility only showed up once I enabled the L2 > cache. I don't know quite what's going on. IIUC, I should move the compatible string to the SoC-specific DTS? And I should remove "sigma,smp8642-ethernet"? >> + phy-connection-type = "rgmii"; >> + max-speed = <1000>; > > You should have a node for the PHY here. I'm using your old ethernet driver for the time being. I just compile the appropriate PHY driver, and everything works as expected. What will the PHY node in DT bring? >> +&intc { >> + compatible = "sigma,smp8758-intc", "sigma,smp8642-intc"; > > Wrong place for the compatible string. IIUC, I should move the compatible string to the SoC-specific DTS? Regards.
Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes: > On 02/11/2015 17:01, Måns Rullgård wrote: > >> There are about a dozen more clocks that will be needed eventually. Do >> you have a plan for how to add them? (My driver already has support for >> most of them.) > > Can you tell me which clocks (for which device) you've needed on the smp8759? For the bare minimum functionality, none. If you want USB or SATA, you'll need those clocks defined. All the media processing has a slew of clocks as well. >>> + periphclk: periphclk { >> >> Why is this not in the clocks block above? > > It was something the clk maintainer said that made me move it, but I can't > find it anymore. I can move it back if that's the consensus. Wait and see what others say. >>> + compatible = "fixed-factor-clock"; >>> + clocks = <&clkgen 0>; >>> + clock-mult = <1>; >>> + clock-div = <2>; >> >> Some Sigma source code I found on the Internet uses a divisor of 3. >> Which is correct? > > I was told 2. OK. >>> + soc { >>> + compatible = "simple-bus"; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + ranges; >> >> Put interrupt-parent = <&irq0> here and save repeating it for each device. > > Each device can have either irq0, irq1, or irq2 as the parent, right? > The old code tried to do IRQ load-balancing "by hand". I had the vague > idea that I would set some devices to irq0, others to irq1, and have > irq_i interrupt CPU_i. Does that make no sense? Which devices to assign to which CPU would depend on the expected usage, something only known at the board level at best. I think it's better to have them all default to irq0 here and let boards override if necessary. >>> + tick-counter@10048 { >>> + compatible = "sigma,tick-counter"; >> >> This compatible name is too vague. What if the next Sigma chip has a >> completely different counter? > > When this happens, I could switch to the generic method you've proposed. This name would still become misleading, and you're not allowed to change a DT binding incompatibly once it's been established. >>> + eth0: ethernet@26000 { >>> + reg = <0x26000 0x800>; >>> + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; >>> + interrupt-parent = <&irq0>; >>> + clocks = <&clkgen 1>; >>> + }; >> >> Missing compatible string. > > It's not missing, it's elsewhere. > (But maybe I did it wrong.) > >>> + intc: interrupt-controller@6e000 { >>> + reg = <0x6e000 0x400>; >>> + ranges = <0 0x6e000 0x400>; >>> + interrupt-parent = <&gic>; >>> + interrupt-controller; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >> >> Missing compatible string. >> >>> + irq0: irq0@6e000 { >> >> The node name should be interrupt-controller@000, similarly below. > > <confused> I changed that a long time ago, and Arnd didn't flag it. > I'll put whatever the arm-soc maintainers say. They usually point to the ePAPR spec, which says interrupt controller nodes should be called interrupt-controller@<addr>. It also says the <addr> following the @ should be the same as the first <reg> address, which here is the offset from the base address. >>> + cpus { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + enable-method = "sigma,tango4-smp"; >> >> This enable-method is too vague. The next chip might be different. > > What string do you propose? > What if I don't expect any other tango4 chip? Expectations are often wrong. Use an actual chip number. >> The device tree should mention the SCU. > > I left it out because I thought it was the firmware's responsibility. > I will double-check with the firmware author. It's still there, and the kernel might want to at least check how it's configured. >>> +ð0 { >>> + compatible = "sigma,smp8758-ethernet", "sigma,smp8734-ethernet", "sigma,smp8642-ethernet", "aurora,nb8800"; >> >> It's odd to specify the compatible string here. It certainly won't >> change between different boards using the same chip. Also, in the >> latest version of my driver, tango3 and tango4 are unfortunately not >> compatible. The incompatibility only showed up once I enabled the L2 >> cache. I don't know quite what's going on. > > IIUC, I should move the compatible string to the SoC-specific DTS? > And I should remove "sigma,smp8642-ethernet"? > >>> + phy-connection-type = "rgmii"; >>> + max-speed = <1000>; >> >> You should have a node for the PHY here. > > I'm using your old ethernet driver for the time being. I just compile the > appropriate PHY driver, and everything works as expected. What will the > PHY node in DT bring? The new driver requires it for starters. Also, the probing acts oddly on my 8642 board, so it's probably best to avoid. >>> +&intc { >>> + compatible = "sigma,smp8758-intc", "sigma,smp8642-intc"; >> >> Wrong place for the compatible string. > > IIUC, I should move the compatible string to the SoC-specific DTS? > > Regards. >
On 02/11/15 07:18, Marc Gonzalez wrote: > This device tree was tested on a Sigma Designs SMP8758 Vantage-1172 > development board. > > Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> > --- > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/tango4-common.dtsi | 121 ++++++++++++++++++++++++++++++ > arch/arm/boot/dts/tango4-smp8758.dtsi | 30 ++++++++ > arch/arm/boot/dts/tango4-vantage-1172.dts | 24 ++++++ > 4 files changed, 177 insertions(+) > create mode 100644 arch/arm/boot/dts/tango4-common.dtsi > create mode 100644 arch/arm/boot/dts/tango4-smp8758.dtsi > create mode 100644 arch/arm/boot/dts/tango4-vantage-1172.dts Since you are introducing DTS with compatible strings etc. you need to document these in Documentation/devicetree/bindings/ as well for people to know how to write their own for their Tango4-based designs. > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 246473a244f6..2499295051d5 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -605,6 +605,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ > dtb-$(CONFIG_MACH_SUN9I) += \ > sun9i-a80-optimus.dtb \ > sun9i-a80-cubieboard4.dtb > +dtb-$(CONFIG_ARCH_TANGOX) += \ > + tango4-vantage-1172.dtb > dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ > tegra20-harmony.dtb \ > tegra20-iris-512.dtb \ > diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi > new file mode 100644 > index 000000000000..90e9a6e736ae > --- /dev/null > +++ b/arch/arm/boot/dts/tango4-common.dtsi > @@ -0,0 +1,121 @@ > +/* > + * Derived from Mans Rullgard's Tango3 DT > + * https://github.com/mansr/linux-tangox > + */ Most DTSes these days contain a proper license, typically BSD, yours should have one too. > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + > + clocks { > + ranges; > + #address-cells = <1>; > + #size-cells = <1>; > + > + xtal: xtal { > + compatible = "fixed-clock"; > + clock-frequency = <27000000>; > + #clock-cells = <0>; > + }; > + > + clkgen: clkgen@10000 { > + compatible = "sigma,tango4-clkgen"; > + reg = <0x10000 0x40>; > + clocks = <&xtal>; > + clock-output-names = "cpuclk", "sysclk"; > + #clock-cells = <1>; > + }; > + }; Do not you have some sort of internal bus/bridge which maps these ARM peripherals to your SoC? You have a simple-bus node later on for your internal and own IPs, it would seem logical to have such a thing here as well for these ARM peripherals. [snip] > diff --git a/arch/arm/boot/dts/tango4-smp8758.dtsi b/arch/arm/boot/dts/tango4-smp8758.dtsi > new file mode 100644 > index 000000000000..4eb23a12e27f > --- /dev/null > +++ b/arch/arm/boot/dts/tango4-smp8758.dtsi > @@ -0,0 +1,30 @@ > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "sigma,tango4-smp"; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + reg = <0>; Missing next-level-cache property and 'enable-method' property.
Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes: >>> + compatible = "fixed-factor-clock"; >>> + clocks = <&clkgen 0>; >>> + clock-mult = <1>; >>> + clock-div = <2>; >> >> Some Sigma source code I found on the Internet uses a divisor of 3. >> Which is correct? > > I was told 2. Just to be sure, I measured it. It's 2.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 246473a244f6..2499295051d5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -605,6 +605,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_ARCH_TANGOX) += \ + tango4-vantage-1172.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-harmony.dtb \ tegra20-iris-512.dtb \ diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi new file mode 100644 index 000000000000..90e9a6e736ae --- /dev/null +++ b/arch/arm/boot/dts/tango4-common.dtsi @@ -0,0 +1,121 @@ +/* + * Derived from Mans Rullgard's Tango3 DT + * https://github.com/mansr/linux-tangox + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + clocks { + ranges; + #address-cells = <1>; + #size-cells = <1>; + + xtal: xtal { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + #clock-cells = <0>; + }; + + clkgen: clkgen@10000 { + compatible = "sigma,tango4-clkgen"; + reg = <0x10000 0x40>; + clocks = <&xtal>; + clock-output-names = "cpuclk", "sysclk"; + #clock-cells = <1>; + }; + }; + + gic: interrupt-controller@20001000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x20001000 0x1000>, <0x20000100 0x0100>; + }; + + l2cc: l2-cache-controller@20100000 { + compatible = "arm,pl310-cache"; + reg = <0x20100000 0x1000>; + cache-level = <2>; + cache-unified; + }; + + periphclk: periphclk { + compatible = "fixed-factor-clock"; + clocks = <&clkgen 0>; + clock-mult = <1>; + clock-div = <2>; + #clock-cells = <0>; + }; + + twd-timer@20000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20000600 0x10>; + interrupts = <GIC_PPI 13 0xf04>; + interrupt-parent = <&gic>; + clocks = <&periphclk>; + always-on; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + tick-counter@10048 { + compatible = "sigma,tick-counter"; + reg = <0x10048 0x4>; + clocks = <&xtal>; + }; + + uart: serial@10700 { + compatible = "ralink,rt2880-uart"; + reg = <0x10700 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irq0>; + clock-frequency = <7372800>; + reg-shift = <2>; + }; + + eth0: ethernet@26000 { + reg = <0x26000 0x800>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irq0>; + clocks = <&clkgen 1>; + }; + + intc: interrupt-controller@6e000 { + reg = <0x6e000 0x400>; + ranges = <0 0x6e000 0x400>; + interrupt-parent = <&gic>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <1>; + + irq0: irq0@6e000 { + reg = <0x000 0x100>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + }; + + irq1: irq1@6e100 { + reg = <0x100 0x100>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + }; + + irq2: irq2@6e300 { + reg = <0x300 0x100>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tango4-smp8758.dtsi b/arch/arm/boot/dts/tango4-smp8758.dtsi new file mode 100644 index 000000000000..4eb23a12e27f --- /dev/null +++ b/arch/arm/boot/dts/tango4-smp8758.dtsi @@ -0,0 +1,30 @@ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "sigma,tango4-smp"; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-affinity = <&cpu0>, <&cpu1>; + interrupt-parent = <&gic>; + interrupts = + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/tango4-vantage-1172.dts b/arch/arm/boot/dts/tango4-vantage-1172.dts new file mode 100644 index 000000000000..22de3624ed97 --- /dev/null +++ b/arch/arm/boot/dts/tango4-vantage-1172.dts @@ -0,0 +1,24 @@ +/dts-v1/; + +#include "tango4-smp8758.dtsi" +#include "tango4-common.dtsi" + +/ { + model = "Sigma Designs SMP8758 Vantage-1172 dev board"; + compatible = "sigma,vantage-1172", "sigma,smp8758", "sigma,tango4"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; /* 2 GB */ + }; +}; + +ð0 { + compatible = "sigma,smp8758-ethernet", "sigma,smp8734-ethernet", "sigma,smp8642-ethernet", "aurora,nb8800"; + phy-connection-type = "rgmii"; + max-speed = <1000>; +}; + +&intc { + compatible = "sigma,smp8758-intc", "sigma,smp8642-intc"; +};
This device tree was tested on a Sigma Designs SMP8758 Vantage-1172 development board. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/tango4-common.dtsi | 121 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/tango4-smp8758.dtsi | 30 ++++++++ arch/arm/boot/dts/tango4-vantage-1172.dts | 24 ++++++ 4 files changed, 177 insertions(+) create mode 100644 arch/arm/boot/dts/tango4-common.dtsi create mode 100644 arch/arm/boot/dts/tango4-smp8758.dtsi create mode 100644 arch/arm/boot/dts/tango4-vantage-1172.dts