| Message ID | 1446637509-6418-2-git-send-email-p.zabel@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Nov 04, 2015 at 12:44:58PM +0100, Philipp Zabel wrote: > From: CK Hu <ck.hu@mediatek.com> > > Add device tree binding documentation for the display subsystem in > Mediatek MT8173 SoCs. > > Signed-off-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> If this wasn't an RFC, I'd ack it. :) One thing you missed below though. > --- > Changes since v4: > - Move device tree binding documentation to > Documentation/devicetree/bindings/display/mediatek > - Clarified display function block nodes are siblings to mmsys > --- > .../bindings/display/mediatek/mediatek,disp.txt | 183 +++++++++++++++++++++ > .../bindings/display/mediatek/mediatek,dpi.txt | 35 ++++ > .../bindings/display/mediatek/mediatek,dsi.txt | 53 ++++++ > 3 files changed, 271 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > new file mode 100644 > index 0000000..cc3d884 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -0,0 +1,183 @@ > +Mediatek display subsystem > +========================== > + > +The Mediatek display subsystem consists of various DISP function blocks in the > +MMSYS register space. The connections between them can be configured by output > +and input selectors in the MMSYS_CONFIG register space and register updates can > +be synchronized to video frame boundaries with help of a DISP_MUTEX function > +block. > + > +All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node. > +For a description of the MMSYS_CONFIG binding, see > +Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt. > + > +DISP function blocks > +==================== > + > +A display stream starts at a source function block that reads pixel data from > +memory and ends with a sink function block that drives pixels on a display > +interface, or writes pixels back to memory. All DISP function blocks have > +their own register space, interrupt, and clock gate. The blocks that can > +access memory additionally have to list the IOMMU and local arbiter they are > +connected to. > + > +For a description of the display interface sink function blocks, see > +Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt and > +Documentation/devicetree/bindings/drm/mediatek/mediatek,dpi.txt. Need to update these paths. > + > +Required properties (all function blocks): > +- compatible: "mediatek,<chip>-disp-<function>", one of > + "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc) > + "mediatek,<chip>-disp-rdma" - read DMA / line buffer > + "mediatek,<chip>-disp-wdma" - write DMA > + "mediatek,<chip>-disp-color" - color processor > + "mediatek,<chip>-disp-aal" - adaptive ambient light controller > + "mediatek,<chip>-disp-gamma" - gamma correction > + "mediatek,<chip>-disp-ufoe" - data compression engine > + "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt > + "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt > + "mediatek,<chip>-disp-mutex" - display mutex > + "mediatek,<chip>-disp-od" - overdrive > +- reg: Physical base address and length of the function block register space > +- interrupts: The interrupt signal from the function block. > +- clocks: device clocks > + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. > +- compatible: "mediatek,<chip>-ddp" > + > +Required properties (DMA function blocks): > +- compatible: Should be one of > + "mediatek,<chip>-disp-ovl" > + "mediatek,<chip>-disp-rdma" > + "mediatek,<chip>-disp-wdma" > +- larb: Should contain a phandle pointing to the local arbiter device as defined > + in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt > +- iommus: required a iommu node > + > +Examples: > + > +mmsys: clock-controller@14000000 { > + compatible = "mediatek,mt8173-mmsys", "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > + #clock-cells = <1>; > +}; > + > +ovl0: ovl@1400c000 { > + compatible = "mediatek,mt8173-disp-ovl"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_OVL0>; > + mediatek,larb = <&larb0>; > +}; > + > +ovl1: ovl@1400d000 { > + compatible = "mediatek,mt8173-disp-ovl"; > + reg = <0 0x1400d000 0 0x1000>; > + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_OVL1>; > + iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_OVL1>; > + mediatek,larb = <&larb4>; > +}; > + > +rdma0: rdma@1400e000 { > + compatible = "mediatek,mt8173-disp-rdma"; > + reg = <0 0x1400e000 0 0x1000>; > + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_RDMA0>; > + mediatek,larb = <&larb0>; > +}; > + > +rdma1: rdma@1400f000 { > + compatible = "mediatek,mt8173-disp-rdma"; > + reg = <0 0x1400f000 0 0x1000>; > + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_RDMA1>; > + mediatek,larb = <&larb4>; > +}; > + > +rdma2: rdma@14010000 { > + compatible = "mediatek,mt8173-disp-rdma"; > + reg = <0 0x14010000 0 0x1000>; > + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_RDMA2>; > + iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_RDMA2>; > + mediatek,larb = <&larb4>; > +}; > + > +wdma0: wdma@14011000 { > + compatible = "mediatek,mt8173-disp-wdma"; > + reg = <0 0x14011000 0 0x1000>; > + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_WDMA0>; > + iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_WDMA0>; > + mediatek,larb = <&larb0>; > +}; > + > +wdma1: wdma@14012000 { > + compatible = "mediatek,mt8173-disp-wdma"; > + reg = <0 0x14012000 0 0x1000>; > + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_WDMA1>; > + iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_WDMA1>; > + mediatek,larb = <&larb4>; > +}; > + > +color0: color@14013000 { > + compatible = "mediatek,mt8173-disp-color"; > + reg = <0 0x14013000 0 0x1000>; > + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > +}; > + > +color1: color@14014000 { > + compatible = "mediatek,mt8173-disp-color"; > + reg = <0 0x14014000 0 0x1000>; > + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_COLOR1>; > +}; > + > +aal@14015000 { > + compatible = "mediatek,mt8173-disp-aal"; > + reg = <0 0x14015000 0 0x1000>; > + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_AAL>; > +}; > + > +gamma@14016000 { > + compatible = "mediatek,mt8173-disp-gamma"; > + reg = <0 0x14016000 0 0x1000>; > + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_GAMMA>; > +}; > + > +ufoe@1401a000 { > + compatible = "mediatek,mt8173-disp-ufoe"; > + reg = <0 0x1401a000 0 0x1000>; > + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_UFOE>; > +}; > + > +dsi0: dsi@1401b000 { > + /* See mediatek,dsi.txt for details */ > +}; > + > +dpi0: dpi@1401d000 { > + /* See mediatek,dpi.txt for details */ > +}; > + > +mutex: mutex@14020000 { > + compatible = "mediatek,mt8173-disp-mutex"; > + reg = <0 0x14020000 0 0x1000>; > + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_MUTEX_32K>; > +}; > + > +od@14023000 { > + compatible = "mediatek,mt8173-disp-od"; > + reg = <0 0x14023000 0 0x1000>; > + clocks = <&mmsys CLK_MM_DISP_OD>; > +}; > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt > new file mode 100644 > index 0000000..b6a7e73 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt > @@ -0,0 +1,35 @@ > +Mediatek DPI Device > +=================== > + > +The Mediatek DPI function block is a sink of the display subsystem and > +provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel > +output bus. > + > +Required properties: > +- compatible: "mediatek,<chip>-dpi" > +- reg: Physical base address and length of the controller's registers > +- interrupts: The interrupt signal from the function block. > +- clocks: device clocks > + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. > +- clock-names: must contain "pixel", "engine", and "pll" > +- port: Output port node with endpoint definitions as described in > + Documentation/devicetree/bindings/graph.txt. This port should be connected > + to the input port of an attached HDMI or LVDS encoder chip. > + > +Example: > + > +dpi0: dpi@1401d000 { > + compatible = "mediatek,mt8173-dpi"; > + reg = <0 0x1401d000 0 0x1000>; > + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DPI_PIXEL>, > + <&mmsys CLK_MM_DPI_ENGINE>, > + <&apmixedsys CLK_APMIXED_TVDPLL>; > + clock-names = "pixel", "engine", "pll"; > + > + port { > + dpi0_out: endpoint { > + remote-endpoint = <&hdmi0_in>; > + }; > + }; > +}; > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > new file mode 100644 > index 0000000..afa7afb > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > @@ -0,0 +1,53 @@ > +Mediatek DSI Device > +=================== > + > +The Mediatek DSI function block is a sink of the display subsystem and can > +drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- > +channel output. > + > +Required properties: > +- compatible: "mediatek,<chip>-dsi" > +- reg: Physical base address and length of the controller's registers > +- interrupts: The interrupt signal from the function block. > +- clocks: device clocks > + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. > +- clock-names: must contain "engine" and "digital". > +- phys: phandle link to the MIPI D-PHY controller. > +- phy-names: must contain "dphy" > +- port: Output port node with endpoint definitions as described in > + Documentation/devicetree/bindings/graph.txt. This port should be connected > + to the input port of an attached DSI panel or DSI-to-eDP encoder chip. > + > +MIPI TX Configuration Module > +============================ > + > +The MIPI TX configuration module controls the MIPI D-PHY. > + > +Required properties: > +- compatible: "mediatek,<chip>-mipi-tx" > +- reg: Physical base address and length of the controller's registers > +- #phy-cells: must be <0>. > + > +Example: > + > +mipi_tx0: mipi-dphy@10215000 { > + compatible = "mediatek,mt8173-mipi-tx"; > + reg = <0 0x10215000 0 0x1000>; > + #phy-cells = <0>; > +}; > + > +dsi0: dsi@1401b000 { > + compatible = "mediatek,mt8173-dsi"; > + reg = <0 0x1401b000 0 0x1000>; > + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>; > + clock-names = "engine", "digital"; > + phys = <&mipi_tx0>; > + phy-names = "dphy"; > + > + port { > + dsi0_out: endpoint { > + remote-endpoint = <&panel_in>; > + }; > + }; > +}; > -- > 2.6.1 >
Am Mittwoch, den 04.11.2015, 21:28 -0600 schrieb Rob Herring: > On Wed, Nov 04, 2015 at 12:44:58PM +0100, Philipp Zabel wrote: > > From: CK Hu <ck.hu@mediatek.com> > > > > Add device tree binding documentation for the display subsystem in > > Mediatek MT8173 SoCs. > > > > Signed-off-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> > > If this wasn't an RFC, I'd ack it. :) One thing you missed below though. Alright, thanks for your help in sorting these bindings out. [...] > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > new file mode 100644 > > index 0000000..cc3d884 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt [...] > > +DISP function blocks > > +==================== > > + > > +A display stream starts at a source function block that reads pixel data from > > +memory and ends with a sink function block that drives pixels on a display > > +interface, or writes pixels back to memory. All DISP function blocks have > > +their own register space, interrupt, and clock gate. The blocks that can > > +access memory additionally have to list the IOMMU and local arbiter they are > > +connected to. > > + > > +For a description of the display interface sink function blocks, see > > +Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt and > > +Documentation/devicetree/bindings/drm/mediatek/mediatek,dpi.txt. > > Need to update these paths. Will do. regards Philipp
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt new file mode 100644 index 0000000..cc3d884 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -0,0 +1,183 @@ +Mediatek display subsystem +========================== + +The Mediatek display subsystem consists of various DISP function blocks in the +MMSYS register space. The connections between them can be configured by output +and input selectors in the MMSYS_CONFIG register space and register updates can +be synchronized to video frame boundaries with help of a DISP_MUTEX function +block. + +All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node. +For a description of the MMSYS_CONFIG binding, see +Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt. + +DISP function blocks +==================== + +A display stream starts at a source function block that reads pixel data from +memory and ends with a sink function block that drives pixels on a display +interface, or writes pixels back to memory. All DISP function blocks have +their own register space, interrupt, and clock gate. The blocks that can +access memory additionally have to list the IOMMU and local arbiter they are +connected to. + +For a description of the display interface sink function blocks, see +Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt and +Documentation/devicetree/bindings/drm/mediatek/mediatek,dpi.txt. + +Required properties (all function blocks): +- compatible: "mediatek,<chip>-disp-<function>", one of + "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc) + "mediatek,<chip>-disp-rdma" - read DMA / line buffer + "mediatek,<chip>-disp-wdma" - write DMA + "mediatek,<chip>-disp-color" - color processor + "mediatek,<chip>-disp-aal" - adaptive ambient light controller + "mediatek,<chip>-disp-gamma" - gamma correction + "mediatek,<chip>-disp-ufoe" - data compression engine + "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt + "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt + "mediatek,<chip>-disp-mutex" - display mutex + "mediatek,<chip>-disp-od" - overdrive +- reg: Physical base address and length of the function block register space +- interrupts: The interrupt signal from the function block. +- clocks: device clocks + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- compatible: "mediatek,<chip>-ddp" + +Required properties (DMA function blocks): +- compatible: Should be one of + "mediatek,<chip>-disp-ovl" + "mediatek,<chip>-disp-rdma" + "mediatek,<chip>-disp-wdma" +- larb: Should contain a phandle pointing to the local arbiter device as defined + in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt +- iommus: required a iommu node + +Examples: + +mmsys: clock-controller@14000000 { + compatible = "mediatek,mt8173-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + #clock-cells = <1>; +}; + +ovl0: ovl@1400c000 { + compatible = "mediatek,mt8173-disp-ovl"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_OVL0>; + mediatek,larb = <&larb0>; +}; + +ovl1: ovl@1400d000 { + compatible = "mediatek,mt8173-disp-ovl"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_OVL1>; + iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_OVL1>; + mediatek,larb = <&larb4>; +}; + +rdma0: rdma@1400e000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_RDMA0>; + mediatek,larb = <&larb0>; +}; + +rdma1: rdma@1400f000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb4>; +}; + +rdma2: rdma@14010000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x14010000 0 0x1000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_RDMA2>; + iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_RDMA2>; + mediatek,larb = <&larb4>; +}; + +wdma0: wdma@14011000 { + compatible = "mediatek,mt8173-disp-wdma"; + reg = <0 0x14011000 0 0x1000>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_WDMA0>; + iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_WDMA0>; + mediatek,larb = <&larb0>; +}; + +wdma1: wdma@14012000 { + compatible = "mediatek,mt8173-disp-wdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_WDMA1>; + iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_WDMA1>; + mediatek,larb = <&larb4>; +}; + +color0: color@14013000 { + compatible = "mediatek,mt8173-disp-color"; + reg = <0 0x14013000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; +}; + +color1: color@14014000 { + compatible = "mediatek,mt8173-disp-color"; + reg = <0 0x14014000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_COLOR1>; +}; + +aal@14015000 { + compatible = "mediatek,mt8173-disp-aal"; + reg = <0 0x14015000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_AAL>; +}; + +gamma@14016000 { + compatible = "mediatek,mt8173-disp-gamma"; + reg = <0 0x14016000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_GAMMA>; +}; + +ufoe@1401a000 { + compatible = "mediatek,mt8173-disp-ufoe"; + reg = <0 0x1401a000 0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_UFOE>; +}; + +dsi0: dsi@1401b000 { + /* See mediatek,dsi.txt for details */ +}; + +dpi0: dpi@1401d000 { + /* See mediatek,dpi.txt for details */ +}; + +mutex: mutex@14020000 { + compatible = "mediatek,mt8173-disp-mutex"; + reg = <0 0x14020000 0 0x1000>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MUTEX_32K>; +}; + +od@14023000 { + compatible = "mediatek,mt8173-disp-od"; + reg = <0 0x14023000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OD>; +}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt new file mode 100644 index 0000000..b6a7e73 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt @@ -0,0 +1,35 @@ +Mediatek DPI Device +=================== + +The Mediatek DPI function block is a sink of the display subsystem and +provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel +output bus. + +Required properties: +- compatible: "mediatek,<chip>-dpi" +- reg: Physical base address and length of the controller's registers +- interrupts: The interrupt signal from the function block. +- clocks: device clocks + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- clock-names: must contain "pixel", "engine", and "pll" +- port: Output port node with endpoint definitions as described in + Documentation/devicetree/bindings/graph.txt. This port should be connected + to the input port of an attached HDMI or LVDS encoder chip. + +Example: + +dpi0: dpi@1401d000 { + compatible = "mediatek,mt8173-dpi"; + reg = <0 0x1401d000 0 0x1000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DPI_PIXEL>, + <&mmsys CLK_MM_DPI_ENGINE>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + + port { + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt new file mode 100644 index 0000000..afa7afb --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -0,0 +1,53 @@ +Mediatek DSI Device +=================== + +The Mediatek DSI function block is a sink of the display subsystem and can +drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- +channel output. + +Required properties: +- compatible: "mediatek,<chip>-dsi" +- reg: Physical base address and length of the controller's registers +- interrupts: The interrupt signal from the function block. +- clocks: device clocks + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- clock-names: must contain "engine" and "digital". +- phys: phandle link to the MIPI D-PHY controller. +- phy-names: must contain "dphy" +- port: Output port node with endpoint definitions as described in + Documentation/devicetree/bindings/graph.txt. This port should be connected + to the input port of an attached DSI panel or DSI-to-eDP encoder chip. + +MIPI TX Configuration Module +============================ + +The MIPI TX configuration module controls the MIPI D-PHY. + +Required properties: +- compatible: "mediatek,<chip>-mipi-tx" +- reg: Physical base address and length of the controller's registers +- #phy-cells: must be <0>. + +Example: + +mipi_tx0: mipi-dphy@10215000 { + compatible = "mediatek,mt8173-mipi-tx"; + reg = <0 0x10215000 0 0x1000>; + #phy-cells = <0>; +}; + +dsi0: dsi@1401b000 { + compatible = "mediatek,mt8173-dsi"; + reg = <0 0x1401b000 0 0x1000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>; + clock-names = "engine", "digital"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + + port { + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +};