| Message ID | 1446485499-26733-3-git-send-email-phil.edworthy@renesas.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Phil, On Mon, Nov 2, 2015 at 6:31 PM, Phil Edworthy <phil.edworthy@renesas.com> wrote: > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > @@ -74,6 +74,15 @@ > clock-frequency = <0>; > }; > > + /* External PCIe clock - can be overridden by the board */ > + pcie_bus_clk: pcie_bus_clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + clock-output-names = "pcie_bus"; > + status = "disabled"; > + }; This is generated by an external clock generator (9FGV0841AKILF on Salvator-X). Hence I think it should be listed with a zero clock-frequency, and be overridden in r8a7795-salvator-x.dts. Hmm, that clock generator generates multiple clocks, so it should have a more complex node. As PCIe always requires a 100 MHz external lock, I guess that's why you modeled it that simpler way? > @@ -682,6 +691,55 @@ > }; > }; > }; > - }; > > + pciec0: pcie@fe000000 { > + compatible = "renesas,pcie-r8a7795"; > + reg = <0 0xfe000000 0 0x80000>; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x00 0xff>; > + device_type = "pci"; > + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 > + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 > + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 > + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; > + /* Map all possible DDR as inbound ranges */ > + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; > + interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, > + <0 117 IRQ_TYPE_LEVEL_HIGH>, > + <0 118 IRQ_TYPE_LEVEL_HIGH>; As there are multiple interrupts, I recommend adding interrupt-names to the DT bindings. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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On Tue, Nov 03, 2015 at 09:13:09AM +0000, Phil Edworthy wrote: > Hi Geert, > > On 03 November 2015 08:01, Geert wrote: > > On Mon, Nov 2, 2015 at 6:31 PM, Phil Edworthy <phil.edworthy@renesas.com> > > wrote: > > > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > > > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > > > @@ -74,6 +74,15 @@ > > > clock-frequency = <0>; > > > }; > > > > > > + /* External PCIe clock - can be overridden by the board */ > > > + pcie_bus_clk: pcie_bus_clk { > > > + compatible = "fixed-clock"; > > > + #clock-cells = <0>; > > > + clock-frequency = <100000000>; > > > + clock-output-names = "pcie_bus"; > > > + status = "disabled"; > > > + }; > > > > This is generated by an external clock generator (9FGV0841AKILF on > > Salvator-X). Hence I think it should be listed with a zero clock-frequency, > > and be overridden in r8a7795-salvator-x.dts. > > > > Hmm, that clock generator generates multiple clocks, so it should have a more > > complex node. As PCIe always requires a 100 MHz external lock, I guess that's > > why you modeled it that simpler way? > Yes and the PCIe driver doesn't care what the clock rate is. We need to ensure > that the external clock is on. > > > > @@ -682,6 +691,55 @@ > > > }; > > > }; > > > }; > > > - }; > > > > > > + pciec0: pcie@fe000000 { > > > + compatible = "renesas,pcie-r8a7795"; > > > + reg = <0 0xfe000000 0 0x80000>; > > > + #address-cells = <3>; > > > + #size-cells = <2>; > > > + bus-range = <0x00 0xff>; > > > + device_type = "pci"; > > > + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 > > > + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 > > > + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 > > > + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; > > > + /* Map all possible DDR as inbound ranges */ > > > + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 > > 0x40000000>; > > > + interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, > > > + <0 117 IRQ_TYPE_LEVEL_HIGH>, > > > + <0 118 IRQ_TYPE_LEVEL_HIGH>; > > > > As there are multiple interrupts, I recommend adding interrupt-names to the > > DT bindings. > I could do, though unfortunately the interrupts are a bit of a jumble. The first > covers MSI and INTx, the second covers DMA and MSI, the third is a mix of PM, > errors and MAC control. I still think we need to use named interrupts. Even if coming up with names for them is a bit of a challenge. -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Simon, On 10 November 2015 01:37, Simon wrote: > On Tue, Nov 03, 2015 at 09:13:09AM +0000, Phil Edworthy wrote: > > Hi Geert, > > > > On 03 November 2015 08:01, Geert wrote: > > > On Mon, Nov 2, 2015 at 6:31 PM, Phil Edworthy > <phil.edworthy@renesas.com> > > > wrote: > > > > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > > > > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > > > > @@ -74,6 +74,15 @@ > > > > clock-frequency = <0>; > > > > }; > > > > > > > > + /* External PCIe clock - can be overridden by the board */ > > > > + pcie_bus_clk: pcie_bus_clk { > > > > + compatible = "fixed-clock"; > > > > + #clock-cells = <0>; > > > > + clock-frequency = <100000000>; > > > > + clock-output-names = "pcie_bus"; > > > > + status = "disabled"; > > > > + }; > > > > > > This is generated by an external clock generator (9FGV0841AKILF on > > > Salvator-X). Hence I think it should be listed with a zero clock-frequency, > > > and be overridden in r8a7795-salvator-x.dts. > > > > > > Hmm, that clock generator generates multiple clocks, so it should have a more > > > complex node. As PCIe always requires a 100 MHz external lock, I guess that's > > > why you modeled it that simpler way? > > Yes and the PCIe driver doesn't care what the clock rate is. We need to ensure > > that the external clock is on. > > > > > > @@ -682,6 +691,55 @@ > > > > }; > > > > }; > > > > }; > > > > - }; > > > > > > > > + pciec0: pcie@fe000000 { > > > > + compatible = "renesas,pcie-r8a7795"; > > > > + reg = <0 0xfe000000 0 0x80000>; > > > > + #address-cells = <3>; > > > > + #size-cells = <2>; > > > > + bus-range = <0x00 0xff>; > > > > + device_type = "pci"; > > > > + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 > > > > + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 > > > > + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 > > > > + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; > > > > + /* Map all possible DDR as inbound ranges */ > > > > + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 > > > 0x40000000>; > > > > + interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, > > > > + <0 117 IRQ_TYPE_LEVEL_HIGH>, > > > > + <0 118 IRQ_TYPE_LEVEL_HIGH>; > > > > > > As there are multiple interrupts, I recommend adding interrupt-names to the > > > DT bindings. > > I could do, though unfortunately the interrupts are a bit of a jumble. The first > > covers MSI and INTx, the second covers DMA and MSI, the third is a mix of PM, > > errors and MAC control. > > I still think we need to use named interrupts. > Even if coming up with names for them is a bit of a challenge. Of course, if I add interrupt names to the DT bindings they will have to be optional since there are Gen2 devices that already use the existing bindings. I'll add this to to todo list... Thanks Phil -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Nov 2, 2015 at 6:31 PM, Phil Edworthy <phil.edworthy@renesas.com> wrote: > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > @@ -682,6 +691,55 @@ > }; > }; > }; > - }; > > + pciec0: pcie@fe000000 { > + compatible = "renesas,pcie-r8a7795"; > + reg = <0 0xfe000000 0 0x80000>; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x00 0xff>; > + device_type = "pci"; > + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 > + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 > + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 > + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; > + /* Map all possible DDR as inbound ranges */ > + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; > + interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, > + <0 117 IRQ_TYPE_LEVEL_HIGH>, > + <0 118 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI ...> (x3) > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; ... &gic GIC_SPI ... > + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; > + clock-names = "pcie", "pcie_bus"; > + power-domains = <&cpg>; > + status = "disabled"; > + }; > + > + pciec1: pcie@ee800000 { > + compatible = "renesas,pcie-r8a7795"; > + reg = <0 0xee800000 0 0x80000>; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x00 0xff>; > + device_type = "pci"; > + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 > + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 > + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 > + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; > + /* Map all possible DDR as inbound ranges */ > + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; > + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>, > + <0 149 IRQ_TYPE_LEVEL_HIGH>, > + <0 150 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI ...> (x3) > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &gic 0 148 IRQ_TYPE_LEVEL_HIGH>; ... &gic GIC_SPI ... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Nov 2, 2015 at 6:31 PM, Phil Edworthy <phil.edworthy@renesas.com> wrote: > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > @@ -74,6 +74,15 @@ > clock-frequency = <0>; > }; > > + /* External PCIe clock - can be overridden by the board */ > + pcie_bus_clk: pcie_bus_clk { Please drop the "_clk" suffix from the device node's name. > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + clock-output-names = "pcie_bus"; The "clock-output-names" property is optional and not needed. Please drop it, the clock will be named after the device node's name. > + status = "disabled"; > + }; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index a433720..bd17f8e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -74,6 +74,15 @@ clock-frequency = <0>; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie_bus"; + status = "disabled"; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -682,6 +691,55 @@ }; }; }; - }; + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a7795"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, + <0 117 IRQ_TYPE_LEVEL_HIGH>, + <0 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a7795"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>, + <0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + }; };
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 60 +++++++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-)