diff mbox

[v2,2/3] ARM: shmobile: r8a7793: Add QSPI device to DT

Message ID 1447291763-27527-3-git-send-email-horms+renesas@verge.net.au (mailing list archive)
State Accepted
Commit 469352ad3c43e689c15cd396cbb750ee831ab63e
Delegated to: Simon Horman
Headers show

Commit Message

Simon Horman Nov. 12, 2015, 1:29 a.m. UTC
Instantiate the QSPI controller in the r8a7793 device tree.

Based similar work for the r8a7794 by by Hisashi Nakamura and
Sergei Shtylyov.

Cc: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/r8a7793.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Comments

Sergei Shtylyov Nov. 12, 2015, 11:50 a.m. UTC | #1
Hello.

On 11/12/2015 4:29 AM, Simon Horman wrote:

> Instantiate the QSPI controller in the r8a7793 device tree.
>
> Based similar work for the r8a7794 by by Hisashi Nakamura and

    Based on, perhaps?

> Sergei Shtylyov.
>
> Cc: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

[...]

MBR, Sergei

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Simon Horman Nov. 13, 2015, 1:11 a.m. UTC | #2
On Thu, Nov 12, 2015 at 02:50:15PM +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 11/12/2015 4:29 AM, Simon Horman wrote:
> 
> >Instantiate the QSPI controller in the r8a7793 device tree.
> >
> >Based similar work for the r8a7794 by by Hisashi Nakamura and
> 
>    Based on, perhaps?

Thanks, I have corrected that and queued-up this patch for v4.5.
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diff mbox

Patch

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 187a82dc7d9f..aa9b64c14a09 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -18,6 +18,10 @@ 
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		spi0 = &qspi;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -222,6 +226,20 @@ 
 		status = "disabled";
 	};
 
+	qspi: spi@e6b10000 {
+		compatible = "renesas,qspi-r8a7793", "renesas,qspi";
+		reg = <0 0xe6b10000 0 0x2c>;
+		interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
+		dmas = <&dmac0 0x17>, <&dmac0 0x18>;
+		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		num-cs = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -463,6 +481,14 @@ 
 				"ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
 				"sata1", "sata0";
 		};
+		mstp9_clks: mstp9_clks@e6150994 {
+			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+			clocks = <&cpg_clocks R8A7793_CLK_QSPI>;
+			#clock-cells = <1>;
+			clock-indices = <R8A7793_CLK_QSPI_MOD>;
+			clock-output-names = "qspi_mod";
+		};
 	};
 
 	ipmmu_sy0: mmu@e6280000 {